Detection device

ABSTRACT

A detection device is provided and including a first detector and a second detector each configured to detect that an object is in contact therewith or in proximity thereto; a signal processor configured to perform signal processing on a detection signal output from the first detector and the second detector; and a selector configured to select one of the first detector and the second detector, and couple the selected one of the first detector and the second detector to the signal processor, wherein the first detector or the second detector is configured to perform self-capacitance detection, the signal processor comprises a self-drive signal transmitter configured to output a self-drive signal for performing the self-capacitance detection, and the selector is configured to output the self-drive signal to a detection electrode of the selected one of the first detector and the second detector, and output the detection signal output from the detection electrode of the selected one of the first detector and the second detector to the signal processor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/826,078, filed on Nov. 29, 2017, which claims priority from JapaneseApplication No. 2016-234238, filed on Dec. 1, 2016, the contents ofwhich are incorporated by reference herein in its entirety.

BACKGROUND

The present disclosure relates to a detection device that can detect anexternal proximate object.

A touch detection device capable of detecting an external proximateobject, or a so-called touch panel, has recently been attractingattention. A touch panel is mounted on or integrated with a displaydevice, such as a liquid crystal display device, which serves as adisplay device with a touch detection function. The display device witha touch detection function displays various kinds of button images andother images on the display device, thereby enabling a user to inputinformation using the touch panel instead of typical mechanical buttons.

In addition to the technologies of the display device with a touchdetection function, there has been developed an electronic apparatusincluding another detector. Another detector is used for detection of afingerprint to cancel a sleep mode of the electronic apparatus, forexample.

Japanese Unexamined Patent Application Publication No. 2013-541780discloses a device having a first handwriting and touch sensor zone, asecond handwriting and touch sensor zone, a first fingerprint sensorzone, and a second fingerprint sensor zone.

Downsizing of an electronic apparatus with a detection device includingtwo detectors has been desired. To downsize the electronic apparatus,the detection device needs to be downsized.

For the foregoing reasons, there is a need for a detection device thatcan be downsized.

SUMMARY

According to an aspect, a detection device includes: a first detectorand a second detector each configured to detect that an object is incontact therewith or in proximity thereto; a signal processor configuredto perform signal processing on a detection signal output from the firstdetector and the second detector; and a selector configured to selectone of the first detector and the second detector, and couple theselected one of the first detector and the second detector to the signalprocessor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a schematic configuration of adetection device according to an embodiment of the present disclosure;

FIG. 2 is a diagram for explaining an example of capacitance generatedin a touch detection device;

FIG. 3 is a diagram for explaining an example of an equivalent circuitof the touch detection device;

FIG. 4 is a diagram illustrating an example of waveforms of a drivesignal and a touch detection signal;

FIG. 5 is a diagram illustrating a state where an object is neither incontact with nor in proximity to a touch detection device for explainingthe basic principle of self-capacitance detection;

FIG. 6 is a diagram illustrating a state where an object is in contactwith or in proximity to the touch detection device for explaining thebasic principle of the self-capacitance detection;

FIG. 7 is a diagram for explaining an example of an equivalent circuitin the self-capacitance detection;

FIG. 8 is a diagram of an example of waveforms of a drive signal and adetection signal in the self-capacitance touch detection;

FIG. 9 is a diagram schematically illustrating a mechanism offingerprint detection performed by a synthesizer;

FIG. 10 is a diagram illustrating an exemplary configuration of thedetection device according to a first embodiment of the presentdisclosure;

FIG. 11 is a sectional view illustrating a schematic sectional structureof a first detector and a display portion of the detection deviceaccording to the first embodiment;

FIG. 12 is a circuit diagram illustrating a pixel array in the displayportion of the detection device according to the first embodiment;

FIG. 13 is a perspective view illustrating an exemplary configuration ofdrive electrodes and touch detection electrodes in the first detector ofthe detection device according to the first embodiment;

FIG. 14 is a plan view illustrating a second detector of the detectiondevice according to the first embodiment;

FIG. 15 is a sectional view illustrating a schematic sectional structureof the second detector of the detection device according to the firstembodiment;

FIG. 16 is a diagram illustrating arrangement of electrodes in thesecond detector of the detection device according to the firstembodiment;

FIG. 17 is a diagram illustrating a circuit configuration of a selectorof the detection device according to the first embodiment;

FIG. 18 is a timing chart of an operation performed by the selector ofthe detection device according to the first embodiment;

FIG. 19 is a timing chart of an operation performed by the selector ofthe detection device according to the first embodiment;

FIG. 20 is a diagram illustrating the detection device according to acomparative example;

FIG. 21 is a diagram illustrating the detection device according amodification of to the first embodiment;

FIG. 22 is a timing chart of an operation performed by the selector ofthe detection device according to the modification of the firstembodiment;

FIG. 23 is a diagram illustrating a circuit configuration of theselector of the detection device according to a second embodiment of thepresent disclosure;

FIG. 24 is a diagram illustrating a state where an object is in contactwith or in proximity to the detection device according to a thirdembodiment of the present disclosure;

FIG. 25 is a side view schematically illustrating the state where theobject is in contact with or in proximity to the detection deviceaccording to the third embodiment; and

FIG. 26 is a timing chart of an operation performed by the selector ofthe detection device according to the third embodiment.

DETAILED DESCRIPTION

Exemplary aspects (embodiments) to embody the present disclosure aredescribed below in greater detail with reference to the accompanyingdrawings. The contents described in the embodiments below are notintended to limit the present disclosure. Components described belowinclude components easily conceivable by those skilled in the art andcomponents substantially identical therewith. Furthermore, thecomponents described below can be appropriately combined. The disclosureis given by way of example only, and appropriate changes made withoutdeparting from the spirit of the invention and easily conceivable bythose skilled in the art naturally fall within the scope of theinvention. To simplify the explanation, the drawings may possiblyillustrate the width, the thickness, the shape, and other elements ofeach portion more schematically than the actual aspect. Thesecomponents, however, are given by way of example only and are notintended to limit interpretation of the present disclosure. In thespecification and the figures, components similar to those previouslydescribed with reference to previous figures are denoted by likereference numerals, and detailed explanation thereof may beappropriately omitted. In this disclosure, when an element is describedas being “on” another element, the element can be directly on the otherelement, or there can be one or more elements between the element andthe other element.

Outline of the Configuration

FIG. 1 is a block diagram illustrating a schematic configuration of adetection device according to an embodiment of the present disclosure.

A detection device 1 includes a first detector SE1, a second detectorSE2, a display portion DP, a selector 4, an analog processor 5, a mutualdrive signal transmitter 7, a display controller 8, and a host HST.

The first detector SE1 detects contact or proximity of an object F1 withor to a detection surface IS of a cover member CG. Specifically, thefirst detector SE1 outputs detection signals Vdet1 according to contactor proximity of the object F1 with or to a plurality of regionsoverlapping with the surface IS in a direction perpendicular to thedetection surface IS.

The object F1 may be a first type of an object that is deformable whenbeing in contact with the detection surface IS, or a second type of anobject that is not deformable or is relatively less deformable than thefirst kind of object when being in contact with the detection surfaceIS. Examples of the first kind of the object may include, but are notlimited to, a finger. Examples of the second kind of the object mayinclude, but are not limited to, a stylus pen made of resin or metal.

The number of objects that can be detected by the first detector SE1 isnot limited to one. The first detector SE1 may detect two or moreobjects.

The object F1 according to the embodiment of the present disclosure is afinger. The first detector SE1 detects the position of contact orproximity (touch coordinates) of the finger F1 serving as the object.

The first detector SE1 is a sensor using a capacitance method, forexample. The capacitance method is a mutual capacitance method or aself-capacitance method, for example.

The second detector SE2 detects contact or proximity of an object F2with or to the second detector SE2. Specifically, the second detectorSE2 outputs detection signals Vdet2 according to contact or proximity ofthe object F2 with or to a plurality of regions overlapping with adetection surface of the second detector SE2 in a directionperpendicular to the detection surface.

The object F2 may be the first type of an object that is deformable whenbeing in contact with the second detector SE2 or the second type of anobject that is not deformable or is relatively less deformable than thefirst type of the object when being in contact with the second detectorSE2. Examples of the first kind of the object may include, but are notlimited to, a finger. Examples of the second kind of the object mayinclude, but are not limited to, a stylus pen made of resin or metal.

The number of objects that can be detected by the second detector SE2 isnot limited to one. The second detector SE2 may detect two or moreobjects.

Assume that the object F2 according to the embodiment of the presentdisclosure is a finger, and the second detector SE2 detects afingerprint of the finger F2 serving as the object.

The second detector SE2 is a sensor using the capacitance method, forexample. The capacitance method is the mutual capacitance method or theself-capacitance method, for example.

The display portion DP displays an image toward the detection surfaceIS. Examples of the display portion DP include, but are not limited to,a liquid crystal display device, and an organic electro-luminescence(EL) display device.

The first detector SE1 and the display portion DP may be a so-calledin-cell device in which they are integrated with each other.Alternatively, the first detector SE1 and the display portion DP may bea so-called on-cell device in which the first detector SE1 is mounted onthe display portion DP. Integrating the first detector SE1 and thedisplay portion DP with each other includes a case where part ofmembers, such as substrates and electrodes, are shared by the displayportion DP and the first detector SE1, for example.

The display controller 8 causes the display portion DP to display animage in accordance with control signals supplied from a controller 47in the host HST.

In a case where the first detector SE1 is a sensor using the mutualcapacitance method, the mutual drive signal transmitter 7 outputs, tothe first detector SE1, mutual drive signals Vcomtm1 for mutualcapacitance detection in accordance with control signals supplied fromthe controller 47 in the host HST. In response to the supply of themutual drive signals Vcomtm1, the first detector SE1 outputs, to theselector 4, detection signals Vdet1 based on the principle of the mutualcapacitance detection, which will be described later.

In a case where the second detector SE2 is a sensor using the mutualcapacitance method, the mutual drive signal transmitter 7 outputs, tothe second detector SE2, mutual drive signals Vcomtm2 for mutualcapacitance detection in accordance with control signals supplied fromthe controller 47 in the host HST. In response to the supply of themutual drive signals Vcomtm2, the second detector SE2 outputs, to theselector 4, detection signals Vdet2 based on the principle of the mutualcapacitance detection, which will be described later.

The selector 4 selects one of the first detector SE1 and the seconddetector SE2 in accordance with control signals supplied from thecontroller 47 in the host HST. The selector 4 electrically couples theselected one of the first detector SE1 and the second detector SE2 tothe analog processor 5. The analog processor 5 includes a self-drivesignal transmitter 41.

In a case where the first detector SE1 is a sensor using theself-capacitance method, the self-drive signal transmitter 41 outputs,to the selector 4, self-drive signals Vcomts for self-capacitancedetection in accordance with control signals supplied from thecontroller 47 in the host HST. The selector 4 selects the first detectorSE1 in accordance with the control signals supplied from the controller47 in the host HST, and outputs the self-drive signals Vcomts to thefirst detector SE1. In response to the supply of the self-drive signalsVcomts, the first detector SE1 outputs, to the selector 4, the detectionsignals Vdet1 based on the principle of the self-capacitance detection,which will be described later. The selector 4 outputs the detectionsignals Vdet1 output from the first detector SE1 to the analog processor5.

In a case where the second detector SE2 is a sensor using theself-capacitance method, the self-drive signal transmitter 41 outputs,to the selector 4, self-drive signals Vcomts for self-capacitancedetection in accordance with control signals supplied from thecontroller 47 in the host HST. The selector 4 selects the seconddetector SE2 in accordance with the control signals supplied from thecontroller 47 in the host HST, and outputs the self-drive signals Vcomtsto the second detector SE2. In response to the supply of the self-drivesignals Vcomts, the second detector SE2 outputs, to the selector 4, thedetection signals Vdet2 based on the principle of the self-capacitancedetection, which will be described later. The selector 4 outputs thedetection signals Vdet2 output from the second detector SE2 to theanalog processor 5.

The detection methods employed by the first detector SE1 and the seconddetector SE2 may include the following four cases: the first detectorSE1 employs the mutual capacitance method, and the second detector SE2employs the mutual capacitance method; the first detector SE1 employsthe mutual capacitance method, and the second detector SE2 employs theself-capacitance method; the first detector SE1 employs theself-capacitance method, and the second detector SE2 employs the mutualcapacitance method; and the first detector SE1 employs theself-capacitance method, and the second detector SE2 employs theself-capacitance method.

In a case where both of the first detector SE1 and the second detectorSE2 are sensors using the self-capacitance method, the mutual drivesignal transmitter 7 is not required.

In a case where both of the first detector SE1 and the second detectorSE2 are sensors using the mutual capacitance method, the self-drivesignal transmitter 41 is not required.

The analog processor 5 is a signal processing circuit that performsanalog signal processing on the detection signals Vdet1 and Vdet2. Theanalog processor 5 includes an amplifier 42. The amplifier 42 amplifiesthe detection signals Vdet1 or Vdet2 supplied from the selector 4. Theamplifier 42 may include an analog low-pass filter (LPF) serving as alow-pass analog filter that removes high-frequency components (noisecomponents) included in the detection signals Vdet1 or Vdet2 and outputsthe resultant signals. The analog processor 5 may include the respectiveamplifiers 42 for the detection signals Vdet1 and Vdet2. In other words,the analog processor 5 may include a plurality of amplifiers 42.

The analog processor 5 includes an analog/digital (A/D) converter 43.The A/D converter 43 samples analog signals supplied from the amplifier42 at a timing in accordance with control signals supplied from thecontroller 47 in the host HST, thereby converting the analog signalsinto digital signals.

The host HST includes a signal processor 44, a coordinate extractor 45,and a synthesizer 46 besides the controller 47.

The signal processor 44 includes a digital filter that reduces noisecomponents included in output signals from the A/D converter 43. Thesignal processor 44 is a logic circuit that determines whether theobject F1 is in contact with or in proximity to the first detector SE1or whether the object F2 is in contact with or in proximity to thesecond detector SE2 in accordance with the output signals from the A/Dconverter 43.

The coordinate extractor 45 is a logic circuit that derives detectioncoordinates Vout1 when contact or proximity of a finger is detected bythe signal processor 44. If the first detector SE1 is selected, thecoordinate extractor 45 outputs the detection coordinates Vout1 to theoutside.

If the second detector SE2 is selected, the synthesizer 46 generatestwo-dimensional information Vout2 indicating the shape of the object F2in contact with or in proximity to the second detector SE2, that is, afingerprint, in accordance with the detection signals Vdet2 output fromthe second detector SE2. The synthesizer 46 outputs the two-dimensionalinformation Vout2 to the outside.

Basic Principle of Detection

The first detector SE1 and the second detector SE2 operate based on thebasic principle of the mutual capacitance detection or theself-capacitance detection.

The following describes the basic principle of the mutual capacitancedetection with reference to FIGS. 2 to 4.

FIG. 2 is a diagram for explaining an example of capacitance generatedin a touch detection device. FIG. 3 is a diagram for explaining anexample of an equivalent circuit of the touch detection device. FIG. 4is a diagram illustrating an example of waveforms of a drive signal anda touch detection signal. FIG. 3 also illustrates a detection circuit.

As illustrated in FIG. 2, for example, a capacitance element C1 includesa pair of electrodes, that is, a drive electrode E1 and a touchdetection electrode E2 facing each other with a dielectric D interposedtherebetween. As illustrated in FIG. 3, one end of the capacitanceelement C1 is coupled to an alternating-current (AC) signal source(drive signal source) S, and the other end thereof is coupled to avoltage detector (touch detector) DET. The voltage detector DET is anintegration circuit included in the amplifier 42 illustrated in FIG. 1,for example.

When the AC signal source S applies an AC rectangular wave Sg at apredetermined frequency (e.g., approximately several kilohertz toseveral hundred kilohertz) to the drive electrode E1 (one end of thecapacitance element C1), an output waveform (touch detection signalVdet) appears via the voltage detector DET coupled to the touchdetection electrode E2 (the other end of the capacitance element C1).The AC rectangular wave Sg corresponds to the mutual drive signalsVcomtm1 and Vcomtm2.

In a state where an object is neither in contact with (nor in proximityto) the touch detection electrode E2 (non-contact state), an electriccurrent I₀ according to the capacitance value of the capacitance elementC1 flows in association with charge and discharge of the capacitanceelement C1. As illustrated in FIG. 4, the voltage detector DET convertsfluctuations in the electric current I₀ according to the AC rectangularwave Sg into fluctuations in the voltage (waveform V₀ indicated by thesolid line).

By contrast, in a state where an object is in contact with (or inproximity to) the touch detection electrode E2 (contact state), acapacitance C2 generated by a finger is in contact with or in proximityto the touch detection electrode E2, as illustrated in FIG. 2. As aresult, a fringe capacitance between the drive electrode E1 and thetouch detection electrode E2 is blocked by the capacitance C2, asillustrated in FIG. 2, and the capacitance element C1 acts as acapacitance element C1 a having a capacitance value smaller than that ofthe capacitance element C1. As illustrated in the equivalent circuit inFIG. 3, an electric current I₁ flows through the capacitance element C1a.

As illustrated in FIG. 4, the voltage detector DET converts fluctuationsin the electric current I₁ according to the AC rectangular wave Sg intofluctuations in the voltage (waveform V₁ indicated by the dotted line).In this case, the waveform V₁ has amplitude smaller than that of thewaveform V₀. Consequently, an absolute value |ΔV| of a voltagedifference between the waveform V₀ and the waveform V₁ varies accordingto the influence made by the object. More preferably, the voltagedetector DET performs an operation with a period Reset to reset chargingand discharging of a capacitor in accordance with the frequency of theAC rectangular wave Sg by performing switching in the circuit, so as toaccurately detect the absolute value |ΔV| of the voltage differencebetween the waveform V₀ and the waveform V₁.

The following describes the basic principle of the self-capacitancedetection with reference to FIGS. 5 to 8.

FIG. 5 is a diagram illustrating a state where an object is neither incontact with nor in proximity to a touch detection device for explainingthe basic principle of the self-capacitance detection. FIG. 6 is adiagram illustrating a state where an object is in contact with or inproximity to the touch detection device for explaining the basicprinciple of the self-capacitance detection. FIG. 7 is a diagram forexplaining an example of an equivalent circuit in the self-capacitancedetection. FIG. 8 is a diagram illustrating an example of waveforms of adrive signal and a detection signal in the self-capacitance touchdetection.

In the left part of FIG. 5, in a state where an object is neither incontact with nor in proximity to the detection electrode E1, a detectionelectrode E1 is coupled to a power source Vdd by a switch SW1 but notcoupled to a capacitor Ccr by a switch SW2. In this state, a capacitanceCx1 included in the detection electrode E1 is charged. In the right partof FIG. 5, the power source Vdd is uncoupled from the detectionelectrode E1 by the switch SW1, and the detection electrode E1 iscoupled to the capacitor Ccr by the switch SW2. In this state, thecapacitance Cx1 is discharged via the capacitor Ccr.

In the left part of FIG. 6, in a state where an object is in contactwith or in proximity to the detection electrode E1, the detectionelectrode E1 is coupled to the power source Vdd by the switch SW1 butnot coupled to the capacitor Ccr by the switch SW2. In this state, acapacitance Cx2 generated by the object in proximity to the detectionelectrode E1 is charged in addition to the capacitance Cx1 included inthe detection electrode E1. In the right part of FIG. 6, the powersource Vdd is uncoupled from the detection electrode E1 by the switchSW1, and the detection electrode E1 is coupled to the capacitor Ccr bythe switch SW2. In this state, the capacitance Cx1 and the capacitanceCx2 are discharged via the capacitor Ccr.

The voltage change characteristics of the capacitor Ccr at the time ofdischarge (the state where the object is in contact with or in proximityto the detection electrode E1) illustrated in the right part of FIG. 6are clearly different from those of the capacitor Ccr at the time ofdischarge (the state where the object is neither in contact with nor inproximity to the detection electrode E1) illustrated in the right partof FIG. 5 due to the presence of the capacitance Cx2. Theself-capacitance method determines whether the object is in contact withor in proximity to the detection electrode E1 by utilizing thedifference in the voltage change characteristics caused by the presenceor absence of the capacitance Cx2.

Specifically, an AC rectangular wave Sg (refer to FIG. 8) at apredetermined frequency (e.g., approximately several kilohertz toseveral hundred kilohertz) is applied to the detection electrode E1. Thevoltage detector DET illustrated in FIG. 7 converts fluctuations in theelectric current according to the AC rectangular wave Sg intofluctuations in the voltage (waveforms V₃ and V₄). The voltage detectorDET is an integration circuit included in the amplifier 42 illustratedin FIG. 1, for example.

As described above, the detection electrode E1 can be uncoupled from thepower source Vdd and the capacitor Ccr by the switch SW1 and the switchSW2, respectively. As illustrated in FIG. 8, the AC rectangular wave Sgrises to the voltage level corresponding to a voltage V₀ at time T₀₁. Atthis time, the switch SW1 is turned ON, and the switch SW2 is turnedOFF. As a result, the voltage level of the detection electrode E1 alsorises to the voltage V₀.

Subsequently, the switch SW1 is turned OFF before time T₁₁. While thedetection electrode E1 is in a floating state at this time, the electricpotential of the detection electrode E1 is maintained at V₀ due to thecapacitance Cx1 (refer to FIG. 5) of the detection electrode E1 or thecapacitance (Cx1+Cx2, refer to FIG. 6) obtained by adding thecapacitance Cx2 generated by the object in contact with or in proximityto the detection electrode E1 to the capacitance Cx1 of the detectionelectrode E1. Subsequently, a switch SW3 is turned ON before time T₁₁and turned OFF after a predetermined time has elapsed, thereby resettingthe voltage detector DET. This reset operation makes an output voltageVdet from the voltage detector DET substantially equal to a referencevoltage Vref.

Subsequently, when the switch SW2 is turned ON at time T₁₁, a voltage ofan inversion input portion of the voltage detector DET rises to thevoltage V₀ equal to that of the detection electrode E1. Subsequently,the voltage of the inversion input portion of the voltage detector DETfalls to the reference voltage Vref in accordance with a time constantof the capacitance Cx1 (or Cx1+Cx2) of the detection electrode E1 and acapacitance C5 in the voltage detector DET. At this time, the electriccharge accumulated in the capacitance Cx1 (or Cx1+Cx2) of the detectionelectrode E1 moves to the capacitance C5 in the voltage detector DET. Asa result, the output voltage Vdet from the voltage detector DETincreases.

When the object is not in proximity to the detection electrode E1, theoutput voltage Vdet from the voltage detector DET is represented by awaveform V₃ indicated by the solid line, and Vdet=Cx1×V₀/C5 issatisfied. When the capacitance generated by the influence of the objectis added, the output voltage Vdet from the voltage detector DET isrepresented by a waveform V₄ indicated by the dotted line, andVdet=(Cx1+Cx2)×V₀/C5 is satisfied.

Subsequently, at time T₃₁ after the electric charge in the capacitanceCx1 (or Cx1+Cx2) of the detection electrode E1 sufficiently moves to thecapacitance C5, the switch SW2 is turned OFF, and the switches SW1 andSW3 are turned ON. As a result, the electric potential of the detectionelectrode E1 is reduced to a low level equal to that of the ACrectangular wave Sg, and the voltage detector DET is reset. The timingto turn ON the switch SW1 may be any timing as long as it is after theswitch SW2 is turned OFF and before time Toa. The timing to reset thevoltage detector DET may be any timing as long as it is after the switchSW2 is turned OFF and before time T₁₂.

The operation described above is repeated at a predetermined frequency(e.g., approximately several kilohertz to several hundred kilohertz).The touch detection device thus can determine whether the object ispresent (whether a touch is made) based on the absolute value |ΔV| ofthe difference between the waveform V₃ and the waveform V₄. Asillustrated in FIG. 8, when the object is not in proximity to thedetection electrode E1, the electric potential of the detectionelectrode E1 is represented by the waveform V₁. By contrast, when thecapacitance Cx2 generated by the influence of the object is added, theelectric potential of the detection electrode E1 is represented by awaveform V₂. The touch detection device may determine whether anexternal proximate object is present (whether a touch is made) bymeasuring time until when the waveforms V₁ and V₂ fall to apredetermined threshold voltage VTH.

FIG. 9 is a diagram schematically illustrating a mechanism offingerprint detection performed by the synthesizer. The synthesizer 46combines the detection signals Vdet2 received from a plurality ofdetection electrodes E1, thereby generating two-dimensional informationindicating the shape of an object in contact with or in proximity to thedetection electrodes E1. Specifically, the synthesizer 46, for example,generates a two-dimensional image that shows a difference in detectionintensity corresponding to a difference in intensity of contact with thesecond detector SE2 (refer to FIG. 1), which is caused by unevenness onan object (e.g., a person's finger), as shades of color (e.g., a grayscale). The output signals Vout2 from the host HST including thesynthesizer 46 corresponds to output signals of the two-dimensionalinformation described above, for example.

To simplify the explanation, FIG. 9 illustrates two-gradation detectionmerely indicating whether the object is in contact with or in proximityto the second detector SE2 as an example, but a detection result in eachblock can be represented by a multi-gradation image in the actualconfiguration. In FIG. 9, the object is an object having a doublecircular protrusion. In a case where the object is a person's fingerhaving a fingerprint, the fingerprint is detected as the two-dimensionalinformation. The functions of the synthesizer 46 may be included in acomponent other than the host HST. An external component, for example,may generate the two-dimensional information in accordance with theoutput signals Vout1 from the coordinate extractor 45. The generation ofthe two-dimensional information may be performed by a hardwarecomponent, such as a circuit, or may be performed by softwareprocessing.

First Embodiment

FIG. 10 is a diagram illustrating an exemplary configuration of thedetection device according to a first embodiment of the presentdisclosure. The first detector SE1 according to the first embodiment isa sensor using the mutual capacitance method. The first detector SE1 andthe display portion DP are integrated with each other to constitute aso-called in-cell device. The second detector SE2 is a sensor using theself-capacitance method.

The display portion DP of the detection device 1 includes a firstsubstrate (e.g., a pixel substrate 2) and a second substrate (e.g., acounter substrate 3). The pixel substrate 2 includes a first insulatingsubstrate (e.g., a TFT substrate 21). The counter substrate 3 includes asecond insulating substrate 31. The TFT substrate 21 and the secondinsulating substrate 31 are glass substrates or film substrates, forexample. A drive IC chip (e.g., a chip on glass (COG) 19) is mounted onthe TFT substrate 21. The pixel substrate 2 (TFT substrate 21) has adisplay region Ad of the display portion DP and a frame Gd.

The COG 19 is an IC chip that is a driver mounted on the TFT substrate21, and serves as a control device including circuits required fordriving the display portion DP, such as the display controller 8illustrated in FIG. 1. Because the thirst detector is a sensor using themutual capacitance method, the COG 19 also serves as a control deviceincluding circuits required for driving the first detector SE1, such asthe mutual drive signal transmitter 7 illustrated in FIG. 1.

The COG 19 is coupled to the host HST mounted on a substrate 61 via aprinted circuit board FPC2 provided between the TFT substrate 21 and thesubstrate 61. The printed circuit board FPC2 and the substrate 61 may beflexible printed circuit boards, rigid circuit boards, or rigid flexiblecircuit boards. The COG 19 drives the first detector SE1 and the displayportion DP in accordance with control signals supplied from the hostHST.

Gate drivers 12A and 12B have a function to sequentially select each onehorizontal line to be a target of display drive performed by the displayportion DP in accordance with control signals supplied from the COG 19.

A source driver 13 is a circuit that supplies pixel signals Vpix topixels Pix (sub-pixels SPix), which will be described later, of thedisplay portion DP in accordance with control signals supplied from theCOG 19. The source driver 13 is supplied with 6-bit image signals Vsigof red (R), green (G), and blue (B), for example.

The source driver 13 receives the image signals Vsig from the COG 19 andsupplies them to a source selector 13S. The source driver 13 generatesswitch control signals Vsel required for separating the pixel signalsVpix multiplexed with the image signals Vsig, and supplies the switchcontrol signals to the source selector 13S together with the pixelsignals Vpix. Providing the source selector 13S can reduce the number ofwires between the source driver 13 and the COG 19. The source selector13S is not necessarily provided. Part of control performed by the sourcedriver 13 may be performed by the COG 19, and only the source selector13S may be provided.

Drive electrode drivers 14A and 14B are circuits that supply mutualdrive signals Vcomtm1 for the mutual capacitance detection and a drivevoltage VcomDC for display to drive electrodes COML, which will bedescribed later, of the display portion DP in accordance with controlsignals supplied from the COG 19.

In the detection device 1, the COG 19 may include circuits, such as thedrive electrode drivers 14A and 14B, and the gate drivers 12A and 12B.The COG 19 is merely one example of implementation, and the presentdisclosure is not limited thereto. A component having the same functionsas those of the COG 19 may be mounted on the printed circuit board FPC2as a chip on film or a chip on flexible (COF), for example.

As illustrated in FIG. 10, drive electrode blocks B of the driveelectrodes COML three-dimensionally intersect with touch detectionelectrodes TDL in a direction perpendicular to the surface of the TFTsubstrate 21.

The drive electrodes COML are a plurality of stripe electrode patternsextending in one direction. To perform a touch detection operation, thedrive electrode drivers 14A and 14B sequentially supply the mutual drivesignals Vcomtm1 to the electrode patterns. The drive electrode block Billustrated in FIG. 10 corresponds to a plurality of stripe electrodepatterns of the drive electrodes COML simultaneously supplied with themutual drive signals Vcomtm1.

The drive electrode blocks B (drive electrodes COML) extend in adirection parallel with the short side of the first detector SE1. Thetouch detection electrodes TDL, which will be described later, extend ina direction intersecting with the extending direction of the driveelectrode blocks B. The touch detection electrodes TDL extend in adirection parallel with the long side of the first detector SE1, forexample.

The source selector 13S includes TFT elements, and is formed near thedisplay region Ad on the TFT substrate 21. A multitude of pixels Pix,which will be described later, are arranged in the display region Ad ina matrix (row-column configuration). The frame Gd is a region in whichno pixel Pix is arranged when viewed in the direction perpendicular tothe surface of the TFT substrate 21. The gate drivers 12A and 12B, andthe drive electrode drivers 14A and 14B are arranged in the frame Gd.

The gate drivers 12A and 12B include TFT elements, and are formed on theTFT substrate 21. The gate drivers 12A and 12B sandwich the displayregion Ad in which the sub-pixels Spix (pixels) described later arearranged in a matrix (row-column configuration) so as to drive thesub-pixels Spix (pixels) from both sides of the display region Ad.Scanning lines are arrayed between the gate driver 12A and the gatedriver 12B. In other words, the scanning lines extend in a directionparallel with the extending direction of the drive electrodes COML whenviewed in the direction perpendicular to the surface of the TFTsubstrate 21.

While the present configuration example includes two circuits of thegate drivers 12A and 12B, this is merely one example of a specificconfiguration of the gate driver, and the preset disclosure is notlimited thereto. The gate driver may be one circuit provided at only oneend of the scanning lines, for example.

The drive electrode drivers 14A and 14B include TFT elements, and areformed on the TFT substrate 21. The drive electrode drivers 14A and 14Bare supplied, from the COG 19, with the drive voltage VcomDC for displayvia display wiring LDC, and with the mutual drive signals Vcomtm1 forthe mutual capacitance detection via touch wiring LAC.

The drive electrode drivers 14A and 14B can drive each of the driveelectrode blocks B arranged side by side, from both sides of each driveelectrode block B. The display wiring LDC that supplies the drivevoltage VcomDC for display and the touch wiring LAC that supplies themutual drive signals Vcomtm1 for the mutual capacitance detection arearranged in parallel in the frames Gd. The display wiring LDC isarranged closer to the display region Ad than the touch wiring LAC is.

With this configuration, the drive voltage VcomDC for display suppliedby the display wiring LDC stabilizes the potential state at the ends ofthe display region Ad. Especially, the configuration stabilizes displayin a liquid crystal display device including liquid crystals in alateral electric field mode.

While the present configuration example includes two circuits of thedrive electrode drivers 14A and 14B, this is merely one example of aspecific configuration of the drive electrode driver, and the presentdisclosure is not limited thereto. The drive electrode driver may be onecircuit provided at only one end of the drive electrode blocks B, forexample.

The first detector SE1 outputs the touch detection signals Vdet1 fromthe short side thereof. This configuration facilitates routing of thewiring to couple the first detector SE1 to the selector 4 via a printedcircuit board FPC1 serving as a terminal.

FIG. 11 is a sectional view illustrating a schematic sectional structureof the first detector and the display portion of the detection deviceaccording to the first embodiment. FIG. 12 is a circuit diagramillustrating a pixel array in the display portion of the detectiondevice according to the first embodiment. The first detector SE1 and thedisplay portion DP include the pixel substrate 2, the second substrate(e.g., the counter substrate 3), and a display functional layer (e.g., aliquid crystal layer 6). The counter substrate 3 faces the pixelsubstrate 2 in the direction perpendicular to the surface of the pixelsubstrate 2. The liquid crystal layer 6 is interposed between the pixelsubstrate 2 and the counter substrate 3.

The pixel substrate 2 includes the TFT substrate 21, a plurality ofpixel electrodes 22, a plurality of drive electrodes COML, and aninsulating layer 24. The TFT substrate 21 serves as a circuit board. Thepixel electrodes 22 are arranged in a matrix (row-column configuration)on the TFT substrate 21. The drive electrodes COML are formed betweenthe TFT substrate 21 and the pixel electrodes 22. The insulating layer24 insulates the pixel electrodes 22 from the drive electrodes COML.

TFT elements Tr of the respective sub-pixels SPix illustrated in FIG.12, and wiring including pixel signal lines SGL and scanning signallines GCL are formed on the TFT substrate 21. The pixel signal lines SGLsupply the pixel signals Vpix to the respective pixel electrodes 22illustrated in FIG. 11, and the scanning signal lines GCL drive the TFTelements Tr. The pixel signal lines SGL extend on a plane parallel withthe surface of the TFT substrate 21, and supply the pixel signals Vpixfor displaying an image to the sub-pixels SPix. Each sub-pixel SPixserves as a constituent unit controlled by the pixel signal Vpix. Eachsub-pixel SPix is a region surrounded by the pixel signal lines SGL andthe scanning signal lines GCL, and serves as a constituent unitcontrolled by the TFT element Tr.

As illustrated in FIG. 12, the display portion DP includes a pluralityof sub-pixels SPix arranged in a matrix (row-column configuration). Thesub-pixels SPix each include a TFT element Tr1 and a liquid crystalelement LC. The TFT element Tr1 is a thin-film transistor, and is ann-channel metal oxide semiconductor (MOS) TFT in this example.

One of the source and the drain of the TFT element Tr1 is coupled to thepixel signal line SGL, the gate thereof is coupled to the scanningsignal line GCL, and the other of the source and the drain thereof iscoupled to one end of the liquid crystal element LC. The one end of theliquid crystal element LC is coupled to the drain of the TFT elementTr1, and the other end thereof is coupled to the drive electrode COML,for example. The drive electrodes COML, the insulating layer 24, and thepixel electrodes 22 are sequentially stacked on the TFT substrate 21 inFIG. 11, but the present disclosure is not limited thereto. The stackingorder on the TFT substrate 21 may be the pixel electrodes 22, theinsulating later 24, and the drive electrodes COML. Alternatively, thedrive electrodes COML and the pixel electrodes 22 may be disposed in thesame layer with the insulating later 24 interposed therebetween.

The sub-pixel SPix is coupled to the other sub-pixels SPix belonging tothe same row in the display portion DP by the scanning signal line GCL.The scanning signal lines GCL are coupled to the gate drivers 12A and12B, and are supplied with the scanning signals Vscan from the gatedrivers 12A and 12B.

The sub-pixel SPix is coupled to the other sub-pixels SPix belonging tothe same column in the display portion DP by the pixel signal line SGL.The pixel signal lines SGL are coupled to the source driver 13 andsupplied with the pixel signals Vpix from the source driver 13.

The sub-pixel SPix is also coupled to the other sub-pixels SPixbelonging to the same row in the display portion DP by the driveelectrode COML. The drive electrodes COML are coupled to the driveelectrode drivers 14A and 14B, and are supplied with the drive signalsVcom from the drive electrode drivers 14A and 14B. In other words, onedrive electrode COML is shared by a plurality of sub-pixels SPixbelonging to the same row, in this example.

The extending direction of the drive electrodes COML according to thepresent configuration example is parallel with the extending directionof the scanning signal lines GCL. The extending direction of the driveelectrodes COML is not limited thereto. The extending direction of thedrive electrodes COML may be parallel with the extending direction ofthe pixel signal lines SGL, for example. The extending direction of thetouch detection electrodes TDL is not necessarily parallel with theextending direction of the pixel signal lines SGL. The extendingdirection of the touch detection electrodes TDL may be parallel with theextending direction of the scanning signal lines GCL.

The gate drivers 12A and 12B illustrated in FIG. 10 apply the scanningsignals Vscan to the gates of the TFT elements Tr1 of the pixels Pix viathe scanning signal line GCL illustrated in FIG. 12, therebysequentially selecting one row (one horizontal line) out of thesub-pixels SPix arranged in a matrix (row-column configuration) in thedisplay portion DP as a target of display drive.

The source driver 13 illustrated in FIG. 10 supplies the pixel signalsVpix to the respective sub-pixels SPix constituting one horizontal linesequentially selected by the gate drivers 12A and 12B via the pixelsignal lines SGL illustrated in FIG. 12. These sub-pixels SPix performdisplay for one horizontal line in accordance with the supplied pixelsignals Vpix.

The drive electrode drivers 14A and 14B illustrated in FIG. 10 apply themutual drive signals Vcomtm1 or the drive voltage VcomDC, therebydriving the drive electrodes COML on a block-by-block basis, one blockincluding a predetermined number of drive electrodes COML.

As described above, the gate drivers 12 line-sequentially scan and drivethe scanning signal lines GCL in the display portion DP in atime-division manner, thereby sequentially selecting one horizontalline. The source driver 13 supplies the pixel signals Vpix to thesub-pixels SPix belonging to the horizontal line in the display portionDP, thereby performing display for each horizontal line. To perform thedisplay operation, the drive electrode drivers 14A and 14B apply thedrive voltage VcomDC to the block including the drive electrodes COMLcorresponding to the horizontal line.

The liquid crystal layer 6 modulates light passing therethroughaccording to the state of an electric field. When the drive electrodeCOML is driven, a voltage according to the pixel signals Vpix suppliedto the pixel electrodes 22 is applied to the liquid crystal layer 6,thereby generating an electric field. The liquid crystals included inthe liquid crystal layer 6 are oriented according to the electric field,which modulates light passing through the liquid crystal layer 6.

As described above, the pixel electrodes 22 and the drive electrodesCOML respectively serve as first electrodes and second electrodes, whichgenerate an electric field in the liquid crystal layer 6. In otherwords, the display portion DP serves as a display device that changesthe contents of display according to electric charges applied to thefirst electrodes and the second electrodes. The following describes thepixel electrodes 22 as the first electrodes, and the drive electrodesCOML as the second electrodes, but the pixel electrodes 22 may be thesecond electrodes, and the drive electrodes COML may be the firstelectrodes. Each pixel electrode 22 is provided for at least one pixelPix or one sub-pixel SPix. Each drive electrode COML is provided to atleast a plurality of pixels Pix or a plurality of sub-pixels SPix.

The present configuration example employs a liquid crystal displaydevice, serving as the display portion DP that employs liquid crystalsin the lateral electric field mode, such as the in-plane switching (IPS)mode including the fringe field switching (FFS) mode. An orientationfilm may be disposed between the liquid crystal layer 6 and the pixelsubstrate 2, and between the liquid crystal layer 6 and the countersubstrate 3 illustrated in FIG. 11.

While the display portion DP has the configuration employing the lateralelectric field mode, it may have a configuration employing other displaymodes. The display portion DP, for example, may have a configurationemploying a mode that uses a vertical electric field generated mainlybetween the main surfaces of the substrates, such as the twisted nematic(TN) mode, the optically compensated bend (OCB) mode, and the verticalaligned (VA) mode. In the configuration employing the display mode thatuses a vertical electric field, the pixel substrate 2 may include thepixel electrodes 22, and the counter substrate 3 may include the driveelectrodes COML, for example.

The counter substrate 3 includes the second insulating substrate 31 anda color filter 32 formed on one surface of the second insulatingsubstrate 31. The touch detection electrodes TDL serving as thedetection electrodes of the first detector SE1 are formed on the othersurface of the second insulating substrate 31. A polarization plate 35is disposed on the touch detection electrodes TDL.

The method for mounting the color filter 32 may be a color-filter onarray (COA) method of forming the color filter 32 on the pixel substrate2 serving as an array substrate.

In the color filter 32 illustrated in FIG. 11, color regions of thecolor filter in three colors, e.g., red (R), green (G), and blue (B),are periodically arranged. Color regions 32R, 32G, and 32B in therespective three colors of R, G, and B, are associated with therespective sub-pixels SPix. A set of the color regions 32R, 32G, and 32Bconstitutes one pixel Pix.

The pixels Pix are arranged in a matrix (row-column configuration) in adirection parallel with the scanning signal lines GCL and a directionparallel with the pixel signal lines SGL, thereby constituting thedisplay region Ad, which will be described later. The color filter 32faces the liquid crystal layer 6 in the direction perpendicular to theTFT substrate 21. As described above, the sub-pixels SPix each candisplay a single color.

The color filter 32 may have another combination of colors as long asthe colors are different from one another. The color filter 32 is notnecessarily provided. Specifically, there may be a region without acolor filter 32, that is, there may be a sub-pixel SPix without a color.The number of sub-pixels SPix included in one pixel Pix may be four ormore.

FIG. 13 is a perspective view illustrating an exemplary configuration ofthe drive electrodes and the touch detection electrodes in the firstdetector of the detection device according to the first embodiment. Thedrive electrodes COML according to the present configuration exampleserve as the drive electrodes of the display portion DP and also as thedrive electrodes of the first detector SE1.

The drive electrodes COML face the pixel electrodes 22 in the directionperpendicular to the surface of the TFT substrate 21. The driveelectrodes COML provided to the pixel substrate 2 and the touchdetection electrodes TDL provided to the counter substrate 3 constitutethe first detector SE1.

The touch detection electrodes TDL are stripe electrode patternsextending in a direction intersecting with the extending direction ofthe electrode patterns of the drive electrodes COML. The touch detectionelectrodes TDL face the drive electrodes COML in the directionperpendicular to the surface of the TFT substrate 21. The electrodepatterns of the touch detection electrodes TDL are coupled to theselector 4.

The electrode patterns formed by the drive electrodes COML and the touchdetection electrodes TDL intersecting with each other have a capacitanceat each intersection. In the first detector SE1, the touch detectionelectrodes TDL output the touch detection signals Vdet1 by the driveelectrode drivers 14A and 14B applying the mutual drive signals Vcomtm1to the drive electrodes COML. The first detector SE1 thus performs thetouch detection.

In other words, the drive electrode COML corresponds to the driveelectrode E1 in the basic principle of touch detection illustrated inFIGS. 2 to 4, and the touch detection electrode TDL corresponds to thetouch detection electrode E2. The first detector SE1 detects a touchaccording to the basic principle.

As described above, the first detector SE1 includes the touch detectionelectrodes TDL that generate a capacitance with one of the firstelectrodes and the second electrodes (e.g., the drive electrodes COMLserving as the second electrodes), and performs the touch detectionaccording to a change in the capacitance.

The electrode patterns formed by the drive electrodes COML and the touchdetection electrodes TDL intersecting with each other serve as touchsensors of the capacitance method arranged in a matrix (row-columnconfiguration). By scanning the entire input surface of the firstdetector SE1, the detection device 1 can detect the position and thecontact area where the object F1 is in contact with or in proximity tothe input surface.

Specifically, when the first detector SE1 performs a touch detectionoperation, the drive electrode drivers 14A and 14B line-sequentiallyscan and drive the drive electrode blocks B illustrated in FIG. 10 in atime-division manner, thereby sequentially selecting each one driveelectrode block B (one detection block) of the drive electrodes COML ina scanning direction Scan. Subsequently, in the first detector SE1, thetouch detection electrodes TDL output the touch detection signals Vdet1.The first detector SE1 thus performs the touch detection for onedetection block.

While the relation between the number of the detection blocks and thenumber of lines in display output may be arbitrarily determined, a touchdetection region corresponding to two lines in the display region Adserves as one detection block, according to the first embodiment. Inother words, the relation between the number of detection blocks and anyone of the number of the pixel electrodes, the number of the scanningsignal lines, and the number of the pixel signal lines facing thedetection block may be arbitrarily determined. In the first embodiment,one drive electrode COML faces two pixel electrodes or two scanningsignal lines.

The touch detection electrodes TDL or the drive electrodes COML (driveelectrode blocks B) do not necessarily have a shape divided into aplurality of stripe portions. The touch detection electrodes TDL or thedrive electrodes COML (drive electrode blocks B) may have a comb shape,for example. The touch detection electrodes TDL or the drive electrodesCOML (drive electrode blocks B) simply need to have a shape divided intoa plurality of portions. The shape of slits that divide the driveelectrodes COML may be a straight line or a curved line.

As an example of the operating method of the detection device 1, thedetection device 1 performs a touch detection operation (in a touchdetection period), a fingerprint detection operation (in a fingerprintdetection period), and a display operation (in a display operationperiod) in a time division manner. The detection device 1 may performthe touch detection operation, the fingerprint detection operation, andthe display operation in any division manner.

Referring back to FIG. 10, one of the short sides of the printed circuitboard FPC1 is coupled to a short side of the first detector SE1. Inother words, the printed circuit board FPC1 is coupled to the firstdetector SE1 such that the longitudinal direction of the printed circuitboard FPC1 extends in parallel with the long side of the first detectorSE1. The other of the short sides of the printed circuit board FPC1 iscoupled to the substrate 61. The printed circuit board FPC1 may be aflexible printed circuit board, a rigid circuit board, or a rigidflexible circuit board.

The printed circuit board FPC1 has a protrusion FPC1 a around its centerposition in the longitudinal direction, the protrusion protruding in adirection intersecting with the longitudinal direction. The protrusionFPC1 a is coupled to a substrate 51 of the second detector SE2. Theprinted circuit board FPC1 is provided with the analog processor 5 at aportion farther from the first detector SE1 than the protrusion FPC1 a.The analog processor 5 may be mounted as a semiconductor integratedcircuit device on the printed circuit board FPC1.

While the second detector SE2 partially overlaps with the pixelsubstrate 2 when viewed in a direction perpendicular to the surface ofthe substrate 51, the present disclosure is not limited thereto. Thesecond detector SE2 does not necessarily overlap with the pixelsubstrate 2 when viewed in the direction perpendicular to the surface ofthe substrate 51. In a case where the second detector SE2 partiallyoverlaps with the pixel substrate 2 when viewed in the directionperpendicular to the surface of the substrate 51, the second detectorSE2 may be or may not be in contact with the pixel substrate 2.

The substrate 51 includes a detection region 52 on which a fingerprintis detected, and a frame 53. A plurality of detection electrodes 54 arearranged in a matrix (row-column configuration) in the detection region52. The frame 53 is a region in which no detection electrode 54 isarranged when viewed in the direction perpendicular to the surface ofthe substrate 51.

FIG. 14 is a plan view illustrating the second detector of the detectiondevice according to the first embodiment. FIG. 15 is a sectional viewillustrating a schematic sectional structure of the second detector ofthe detection device according to the first embodiment. Specifically,FIG. 15 is a sectional view illustrating a state where the seconddetector SE2 is accommodated in a housing 101 of an electronicapparatus. The second detector SE2 is embedded in an electronicapparatus, such as a smartphone, and is arranged on the same side (frontsurface side) as that of the display surface of the display portion DPon which an image is displayed. The second detector SE2 is embedded inan opening of the housing 101. When a finger F2 is in contact with or inproximity to the portion provided with the second detector SE2, thesecond detector SE2 detects a fingerprint.

As illustrated in FIGS. 14 and 15, the second detector SE2 includes thesubstrate 51 and the detection electrodes 54 provided to the substrate51. The substrate 51 has a first surface 51 a and a second surface 51 bon the opposite side of the first surface 51 a. The first surface 51 aof the substrate 51 is a detection surface to detect unevenness of thefinger F2 in contact with or in proximity to the second detector SE2.The detection electrodes 54 are provided on the second surface 51 b ofthe substrate 51.

The region in which the detection electrodes 54 are disposed correspondsto the detection region 52 that can detect unevenness of the finger F2.The frame 53 is located outside the detection region 52. The selector 4and the protrusion FPC1 a of the printed circuit board FPC1 are providedin the frame 53.

As illustrated in FIG. 15, the first surface 51 a of the substrate 51may be provided with a protective layer 56 that protects the substrate51, and the second surface 51 b may be provided with a protective layer57. The second surface 51 b of the substrate 51 is further provided withthe selector 4 and is coupled to the protrusion FPC1 a of the printedcircuit board FPC1. The selector 4 may include TFT elements, and beprovided in the frame 53 on the second surface 51 b of the substrate 51.Alternatively, the selector 4 may be disposed as a semiconductorintegrated circuit device in the frame 53 on the second surface 51 b ofthe substrate 51 or on the printed circuit board FPC1. The detectionsignals Vdet2 output from the detection electrodes 54 are output to theselector 4.

The substrate 51 can employ a glass substrate. Employing toughened glassfor the substrate 51, for example, can make the substrate 51 thinnerwhile maintaining its strength. Examples of the toughened glass mayinclude, but are not limited to: chemically toughened glass, on thesurface of which a compressive stress layer is formed by exchangingsodium (Na) ions on the surface of the glass for potassium (K) ionshaving a larger ionic radius; and toughened glass, on the surface ofwhich a compressive stress layer is formed by feeding air to a heatedglass substrate for rapid cooling. The substrate 51 may be made ofsix-face toughened glass.

The detection electrodes 54 are provided on the second surface 51 b ofthe substrate 51. As illustrated in FIG. 14, the detection electrodes 54each have a rectangular shape and are arranged in a matrix (row-columnconfiguration). The detection electrodes 54, for example, are arrayed ata pitch of 50 μm in the row direction, and at a pitch of 50 μm in thecolumn direction. The array pitch in the row direction may be differentfrom that in the column direction. The detection electrodes 54 arrangedin a matrix (row-column configuration) detect a fingerprint of thefinger F2. The detection electrodes 54 each correspond to the detectionelectrode E1 in the basic principle of the self-capacitance fingerprintdetection described above. The detection electrodes 54 can detect afingerprint of a finger in contact with or in proximity to the seconddetector SE2 in accordance with a change in the capacitance of therespective detection electrodes 54. The detection electrodes 54 are madeof a metal material, such as molybdenum (Mo). Alternatively, thedetection electrodes 54 may be made of at least one metal material ofaluminum (Al), copper (Cu), silver (Ag), and an alloy of these metals.

The frame 53 on the second surface 51 b of the substrate 51 is furtherprovided with gate drivers 61A and 61B. The gate drivers 61A and 61Bsequentially select the detection electrodes 54 row by row in accordancewith control signals supplied from the controller 47.

While the present configuration example includes the two circuits, i.e.,the gate drivers 61A and 61B, this is merely one example of a specificconfiguration of the gate driver, and the present disclosure is notlimited thereto. The gate driver may be one circuit provided at only oneside of the frame 53, for example.

As illustrated in FIG. 15, the frame 53 of the substrate 51 is fixed toa stationary part 101 a of the housing 101. The first surface 51 a ofthe substrate 51 is exposed from the opening of the housing 101. Thedetection region 52 overlaps with the opening. When the finger F2 of anoperator is in contact with or in proximity to the opening of thehousing 101, the second detector SE2 can detect a fingerprint of thefinger F2.

As described above, the second detector SE2 has the first surface 51 aserving as the detection surface, and the second surface 51 b on theopposite side of the first surface 51 a. The second surface 51 b isprovided with the detection electrodes 54, the selector 4, and theprotrusion FPC1 a of the printed circuit board FPC1. In fixing thesubstrate 51 to the housing 101, this configuration can reduceconstraints by the unevenness of the selector 4 and that of theprotrusion FPC1 a of the printed circuit board FPC1. In other words,this configuration can simplify the structure of the housing 101 towhich the first surface 51 a side of the substrate 51 is fixed, therebyfacilitating processing of the housing and attachment of the seconddetector SE2 to the housing 101. In addition, since the selector 4 andthe protrusion FPC1 a of the printed circuit board FPC1 are provided onthe second surface 51 b, no conductor including wiring is present on aside closer to the first surface 51 a than the detection electrodes 54.This configuration can reduce detection errors and prevent deteriorationin the detection sensitivity.

FIG. 16 is a diagram illustrating arrangement of electrodes in thesecond detector of the detection device according to the firstembodiment. The second detector SE2 includes the detection electrodes 54and a selector 62.

As illustrated in FIG. 16, the second detector SE2 includes thedetection electrodes 54 arranged in a matrix (row-column configuration).One of the sources and the drains of a plurality of TFT elements Tr2 arecoupled to the respective detection electrodes 54. The TFT element Tr2is a thin-film transistor, and is an n-channel MOS TFT in this example.The other of the sources and the drains of the TFT elements Tr2 arecoupled to respective signal lines H₁, H₂, . . . , and H_(m), and thegates thereof are coupled to respective scanning lines G₁, G₂, . . . ,and G_(q).

The detection electrode 54 is coupled to the other detection electrodes54 belonging to the same row in the second detector SE2 by one of thescanning lines G₁, G₂, . . . , and G_(q). The scanning lines G₁, G₂, . .. , and G_(q) are coupled to the gate drivers 61A and 61B, and aresupplied with scanning signals from the gate drivers 61A and 61B. Thegate drivers 61A and 61B sequentially select the detection electrodes 54row by row in accordance with control signals supplied from thecontroller 47.

The detection electrode 54 is coupled to the other detection electrodes54 belonging to the same column in the second detector SE2 by therespective signal lines H₁, H₂, . . . , and H_(m). The signal lines H₁,H₂, . . . , and H_(m) are coupled to the selector 62, and are suppliedwith the self-drive signals Vcomts from the selector 4 via the selector62.

The selector 62 has a function to output the self-drive signals Vcomtssupplied from the selector 4 to one of the signal lines coupled to thedetection electrodes 54 side of the selector 62 in accordance withcontrol signals supplied from the controller 47.

Specifically, the selector 62 includes connections D₁, D₂, . . . , andD_(r). The connections D₁, D₂, . . . , and D_(r) are each coupled, viaswitches, to the signal lines coupled to respective three detectionelectrodes 54 aligned in the x-direction, for example. The connectionsD₁, D₂, . . . , and D_(r) on the selector 4 side serve as a singlesystem. The connections D₁, D₂, . . . , and D_(r) on the selector 4 sideare coupled to respective wires J₁, J₂, . . . , and J_(r). In theselector 62 according to the first embodiment, the number of wires onthe selector 4 side is equal to the number (r) of the connections D₁,D₂, . . . , and D_(r). The number of wires on the detection electrode 54side is equal to the number (m) of the signal lines H₁, H₂, . . . , andH_(m). In other words, one connection is provided to three signal lines.With this configuration, the selector 62 outputs the self-drive signalVcomts supplied from the selector 4 to any one of up to three detectionelectrodes 54 aligned in the x-direction.

The selector 62 also has a function to output, to the selector 4, thedetection signal Vdet2 supplied via any one of the signal lines coupledto the detection electrode 54 side of the selector, in accordance withcontrol signals supplied from the controller 47. With the configurationin which one connection is provided to three signal lines, the selector62 outputs, to the selector 4, any one of the detection signals Vdet2supplied from up to three detection electrodes 54 aligned in thex-direction.

FIG. 17 is a diagram illustrating a circuit configuration of theselector of the detection device according to the first embodiment. Asillustrated in FIG. 17, the selector 4 includes a first connector 4 a, asecond connector 4 b, a first controller 4 c, and a second controller 4d. The first connector 4 a couples the first detector SE1 to the analogprocessor 5. The second connector 4 b couples the second detector SE2 tothe analog processor 5. The first controller 4 c controls the firstconnector 4 a. The second controller 4 d controls the second connector 4b.

The first connector 4 a is coupled to the first detector SE1 via wiresK₁, K₂, . . . , and K₈. The wires K₁, K₂, . . . , and K₈ are coupled tothe respective touch detection electrodes TDL in the first detector SE1.In other words, the first connector 4 a is coupled to the touchdetection electrodes TDL in the first detector SE1. While the number ofwires K according to the first embodiment is eight, the presentdisclosure is not limited thereto.

The second connector 4 b is coupled to the second detector SE2 via wiresJ₁, J₂, . . . , and J₈. The wires J₁, J₂, . . . , and J₈ are coupled tothe respective connections D₁, D₂, . . . , and D₈ in the selector 62 ofthe second detector SE2. The connections D₁, D₂, . . . , and D₈ arecoupled to the detection electrodes 54. In other words, the secondconnector 4 b is coupled to the detection electrodes 54 in the seconddetector SE2. While the number of wires J according to the firstembodiment is eight, the present disclosure is not limited thereto.

While the number of wires K according to the first embodiment is equalto that of wires J, the present disclosure is not limited thereto. Thenumber of wires K may be different from that of wires J.

The selector 4 is coupled to the host HST via wires L₁, L₄, L₅, and L₆.The wire L₁ is supplied from the host HST with selection signals SEL forselecting the first detector SE1 out of the first detector SE1 and thesecond detector SE2. The wire L₄ is supplied from the host HST withinverted selection signals xSEL for selecting the second detector SE2out of the first detector SE1 and the second detector SE2. According tothe first embodiment, the inverted selection signal xSEL is a logicallyinverted signal of the selection signal SEL.

The wire L₅ is supplied with clock signals CLK from the host HST. Thefirst controller 4 c and the second controller 4 d count the clocksignals CLK to control the first connector 4 a and the second connector4 b, respectively. The first controller 4 c and the second controller 4d are counter circuits or decoder circuits, for example.

The first controller 4 c is coupled to the first connector 4 a via wiresM₁ to M₄. The first controller 4 c sequentially outputs high-levelsignals from the wire M₁ to the wire M₄ in the order of the wire M₁, thewire M₂, the wire M₃, the wire M₄, the wire M₁, . . . in accordance withthe count value of the clock signals CLK. The second controller 4 dsequentially outputs high-level signals from a wire N₁ to a wire N₄ inthe order of the wire N₁, the wire N₂, the wire N₃, the wire N₄, thewire N₁, . . . in accordance with the count value of the clock signalsCLK.

The wire L₆ is supplied from the host HST with reset signals RST forresetting the first controller 4 c and the second controller 4 d. Whenreceiving the reset signals RST, the first controller 4 c and the secondcontroller 4 d reset the count value of the clock signals CLK.

The selector 4 is coupled to the analog processor 5 via wires L₂ and L₃.The analog processor 5 according to the first embodiment includes twoanalog processing channels that can input or output two analog signalssimultaneously. Specifically, the self-drive signal transmitter 41(refer to FIG. 1) in the analog processor 5 includes two analog outputchannels, and can output two self-drive signals Vcomts(1) and Vcomts(2)simultaneously. The amplifier 42 (refer to FIG. 1) in the analogprocessor 5 includes two analog input channels, and can simultaneouslyamplify detection signals Vdet1(1) and Vdet1(2), or detection signalsVdet2(1) and Vdet2(2). The A/D converter 43 (refer to FIG. 1) in theanalog processor 5 includes two A/D conversion circuits, and cansimultaneously convert two analog signals output from the amplifier 42into digital signals.

The wire L₂ is coupled to one of the analog processing channels of theanalog processor 5, and the wire L₃ is coupled to the other of theanalog processing channels of the analog processor 5. The wire L₂ issupplied with the self-drive signals Vcomts(1) for detecting aself-capacitance from the one of the analog output channels of theself-drive signal transmitter 41. The wire L₃ is supplied with theself-drive signals Vcomts(2) for detecting a self-capacitance from theother of the analog output channels of the self-drive signal transmitter41.

In step with the analog processor 5 including the two analog processingchannels, the first connector 4 a includes a first circuit 4 a 1 and asecond circuit 4 a 2 that couple the first detector SE1 to the analogprocessor 5. The first circuit 4 a 1 couples a first wire group 111including the wires K₁ to K₄ to the one of the analog processingchannels of the analog processor 5. The second circuit 4 a 2 couples asecond wire group 112 including the wires K₅ to K₈ to the other of theanalog processing channels of the analog processor 5.

Specifically, the first circuit 4 a 1 sequentially selects any one ofthe wires K₁ to K₄ of the first wire group 111 in accordance withsignals supplied to the wires M₁ to M₄, and couples the selected one tothe wire L₂. As a result, the detection signals Vdet1(1) supplied fromthe first detector SE1 to the wires K₁ to K₄ are sequentially suppliedto the one of the analog input channels of the amplifier 42 in theanalog processor 5.

The second circuit 4 a 2 sequentially selects any one of the wires K₅ toK₈ of the second wire group 112 in accordance with signals supplied tothe wires M₁ to M₄, and couples the selected one to the wire L₃. As aresult, the detection signals Vdet1(2) supplied from the first detectorSE1 to the wires K₅ to K₈ are sequentially supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

The first connector 4 a simultaneously couples two groups of the touchdetection electrodes TDL in the first detector SE1 to the respective twoanalog processing channels of the analog processor 5.

In step with the analog processor 5 including the two analog processingchannels, the second connector 4 b includes a third circuit 4 b 1 and afourth circuit 4 b 2 that couple the second detector SE2 to the analogprocessor 5. The third circuit 4 b 1 couples a third wire group 113including the wires J₁ to J₄ to the one of the analog processingchannels of the analog processor 5. The fourth circuit 4 b 2 couples afourth wire group 114 including the wires J₅ to J₈ to the other of theanalog processing channels of the analog processor 5.

Specifically, the third circuit 4 b 1 sequentially selects any one ofthe wires J₁ to J₄ of the third wire group 113 in accordance withsignals supplied to the wires N₁ to N₄, and couples the selected one tothe wire L₂. As a result, the self-drive signals Vcomts(1) supplied fromthe one of the analog output channels of the self-drive signaltransmitter 41 to the wire L₂ are sequentially supplied to the wires J₁to J₄. The detection signals Vdet2(1) supplied from the second detectorSE2 to the wires J₁ to J₄ are sequentially supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

The fourth circuit 4 b 2 sequentially selects any one of the wires J₅ toJ₈ of the fourth wire group 114 in accordance with signals supplied tothe wires N₁ to N₄, and couples the selected one to the wire L₃. As aresult, the self-drive signals Vcomts(2) supplied from the other of theanalog output channels of the self-drive signal transmitter 41 to thewire L₃ are sequentially supplied to the wires J₅ to J₈. The detectionsignals Vdet2(2) supplied from the second detector SE2 to the wires J₅to J₈ are sequentially supplied to the other of the analog inputchannels of the amplifier 42 in the analog processor 5.

The second connector 4 b simultaneously couples two groups of thedetection electrodes 54 in the second detector SE2 to the respective twoanalog processing channels of the analog processor 5.

The first circuit 4 a 1 includes N-channel transistors 71 and 81 to 84.The gate of the transistor 71 is coupled to the wire L₁. When receivinghigh-level selection signals SEL from the host HST via the wire L₁, thetransistor 71 is turned ON.

One of the source and the drain of the transistor 71 is coupled to theone of the analog processing channels of the analog processor 5 via thewire L₂.

One of the sources and the drains of the transistors 81 to 84 arecoupled to the other of the source and the drain of the transistor 71.The other of the source and the drain of the transistor 81 is coupled tothe wire K₁. The other of the source and the drain of the transistor 82is coupled to the wire K₂. The other of the source and the drain of thetransistor 83 is coupled to the wire K₃. The other of the source and thedrain of the transistor 84 is coupled to the wire K₄.

The second circuit 4 a 2 includes N-channel transistors 72 and 85 to 88.The gate of the transistor 72 is coupled to the wire L₁. When receivinghigh-level selection signals SEL from the host HST via the wire L₁, thetransistor 72 is turned ON.

One of the source and the drain of the transistor 72 is coupled to theother of the analog processing channels of the analog processor 5 viathe wire L₃.

One of the sources and the drains of the transistors 85 to 88 arecoupled to the other of the source and the drain of the transistor 72.The other of the source and the drain of the transistor 85 is coupled tothe wire K₅. The other of the source and the drain of the transistor 86is coupled to the wire K₆. The other of the source and the drain of thetransistor 87 is coupled to the wire K₇. The other of the source and thedrain of the transistor 88 is coupled to the wire K₈.

The gates of the transistors 81 and 85 are coupled to the firstcontroller 4 c via the wire M₁. When high-level signals are suppliedfrom the first controller 4 c to the wire M₁, the transistors 81 and 85are turned ON.

The gates of the transistors 82 and 86 are coupled to the firstcontroller 4 c via the wire M₂. When high-level signals are suppliedfrom the first controller 4 c to the wire M₂, the transistors 82 and 86are turned ON.

The gates of the transistors 83 and 87 are coupled to the firstcontroller 4 c via the wire M₃. When high-level signals are suppliedfrom the first controller 4 c to the wire M₃, the transistors 83 and 87are turned ON.

The gates of the transistors 84 and 88 are coupled to the firstcontroller 4 c via the wire M₄. When high-level signals are suppliedfrom the first controller 4 c to the wire M₄, the transistors 84 and 88are turned ON.

The third circuit 4 b 1 includes N-channel transistors 73 and 91 to 94.The gate of the transistor 73 is coupled to the wire L₄. When receivinghigh-level inverted selection signals xSEL from the host HST via thewire L₄, the transistor 73 is turned ON.

One of the source and the drain of the transistor 73 is coupled to theone of the analog processing channels of the analog processor 5 via thewire L₂.

One of the sources and the drains of the transistors 91 to 94 arecoupled to the other of the source and the drain of the transistor 73.The other of the source and the drain of the transistor 91 is coupled tothe wire J₁. The other of the source and the drain of the transistor 92is coupled to the wire J₂. The other of the source and the drain of thetransistor 93 is coupled to the wire J₃. The other of the source and thedrain of the transistor 94 is coupled to the wire J₄.

The fourth circuit 4 b 2 includes N-channel transistors 74 and 95 to 98.The gate of the transistor 74 is coupled to the wire L₄. When receivinghigh-level inverted selection signals xSEL from the host HST via thewire L₄, the transistor 74 is turned ON.

One of the source and the drain of the transistor 74 is coupled to theother of the analog processing channels of the analog processor 5 viathe wire L₃.

One of the sources and the drains of the transistors 95 to 98 arecoupled to the other of the source and the drain of the transistor 74.The other of the source and the drain of the transistor 95 is coupled tothe wire J₅. The other of the source and the drain of the transistor 96is coupled to the wire J₆. The other of the source and the drain of thetransistor 97 is coupled to the wire J₇. The other of the source and thedrain of the transistor 98 is coupled to the wire J₈.

The gates of the transistors 91 and 95 are coupled to the secondcontroller 4 d via the wire N₁. When high-level signals are suppliedfrom the second controller 4 d to the wire the transistors 91 and 95 areturned ON.

The gates of the transistors 92 and 96 are coupled to the secondcontroller 4 d via the wire N₂. When high-level signals are suppliedfrom the second controller 4 d to the wire N₂, the transistors 92 and 96are turned ON.

The gates of the transistors 93 and 97 are coupled to the secondcontroller 4 d via the wire N₃. When high-level signals are suppliedfrom the second controller 4 d to the wire N₃, the transistors 93 and 97are turned ON.

The gates of the transistors 94 and 98 are coupled to the secondcontroller 4 d via the wire N₄. When high-level signals are suppliedfrom the second controller 4 d to the wire N₄, the transistors 94 and 98are turned ON.

FIG. 18 is a timing chart of an operation performed by the selector ofthe detection device according to the first embodiment. Specifically,FIG. 18 is a timing chart when the selector 4 selects the first detectorSE1 out of the first detector SE1 and the second detector SE2, andcouples the selected first detector SE1 to the analog processor 5.

As illustrated in FIG. 18, when the selection signal SEL supplied fromthe host HST changes from the low level to the high level at timing to,the transistors 71 and 72 in the first connector 4 a are turned ON. Whenthe inverted selection signal xSEL supplied from the host HST changesfrom the high level to the low level, the transistors 73 and 74 in thesecond connector 4 b are turned OFF. When the reset signal RST changesfrom the high level to the low level, the resetting of the count valuein the first controller 4 c is cancelled.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₁, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₁ in accordance with the count value (=1). As a result, thetransistors 81 and 85 in the first connector 4 a are turned ON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 (refer toFIG. 10) to one drive electrode block B in the first detector SE1changes to the high level at the next timing t₂, the detection signalVdet1 described in the principle of the mutual capacitance detection(refer to FIGS. 2 to 4) appears in the touch detection electrode TDL.Because the transistors 81 and 71 are turned ON at the timing t₂, thedetection signal Vdet1(1) appearing in the wire K₁ is supplied to theone of the analog input channels of the amplifier 42 in the analogprocessor 5. Because the transistors 85 and 72 are also turned ON at thetiming t₂, the detection signal Vdet1(2) appearing in the wire K₅ issupplied to the other of the analog input channels of the amplifier 42in the analog processor 5.

The detection signals Vdet1(1) and Vdet1(2) illustrated in FIG. 18 donot indicate actual waveforms appearing in the touch detection electrodeTDL, but indicate output waveforms in the voltage detector DET in theamplifier 42.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₃, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₂ in accordance with the count value (=2). As a result, thetransistors 82 and 86 in the first connector 4 a are turned ON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₄, the detection signal Vdet1 described in theprinciple of the mutual capacitance detection appears in the touchdetection electrode TDL. Because the transistors 82 and 71 are turned ONat the timing t₄, the detection signal Vdet1(1) appearing in the wire K₂is supplied to the one of the analog input channels of the amplifier 42in the analog processor 5. Because the transistors 86 and 72 are alsoturned ON at the timing t₄, the detection signal Vdet1(2) appearing inthe wire K₁ is supplied to the other of the analog input channels of theamplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₅, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₃ in accordance with the count value (=3). As a result, thetransistors 83 and 87 in the first connector 4 a are turned ON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₆, the detection signal Vdet1 described in theprinciple of the mutual capacitance detection appears in the touchdetection electrode TDL. Because the transistors 83 and 71 are turned ONat the timing t₆, the detection signal Vdet1(1) appearing in the wire K₃is supplied to the one of the analog input channels of the amplifier 42in the analog processor 5. Because the transistors 87 and 72 are alsoturned ON at the timing t₆, the detection signal Vdet1(2) appearing inthe wire K₇ is supplied to the other of the analog input channels of theamplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₇, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₄ in accordance with the count value (=4). As a result, thetransistors 84 and 88 in the first connector 4 a are turned ON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₈, the detection signal Vdet1 described in theprinciple of the mutual capacitance detection appears in the touchdetection electrode TDL. Because the transistors 84 and 71 are turned ONat the timing t₈, the detection signal Vdet1(1) appearing in the wire K₄is supplied to the one of the analog input channels of the amplifier 42in the analog processor 5. Because the transistors 88 and 72 are alsoturned ON at the timing t₈, the detection signal Vdet1(2) appearing inthe wire K₈ is supplied to the other of the analog input channels of theamplifier 42 in the analog processor 5.

From the timing t₁ to the timing t₈, the detection device 1 can performdetection for one drive electrode block B in the first detector SE1. Byrepeating the processing performed from the timing t₁ to the timing t₈the same number of times as the number of the drive electrode blocks B,the detection device 1 can perform detection for the entire detectionregion of the first detector SE1.

FIG. 19 is a timing chart of an operation performed by the selector ofthe detection device according to the first embodiment. Specifically,FIG. 19 is a timing chart when the selector 4 selects the seconddetector SE2 out of the first detector SE1 and the second detector SE2,and couples the selected second detector SE2 to the analog processor 5.

As illustrated in FIG. 19, when the selection signal SEL supplied fromthe host HST changes from the high level to the low level at timing t₂₀,the transistors 71 and 72 in the first connector 4 a are turned OFF.When the inverted selection signal xSEL supplied from the host HSTchanges from the low level to the high level, the transistors 73 and 74in the second connector 4 b are turned ON. When the reset signal RSTchanges from the high level to the low level, the resetting of the countvalue in the second controller 4 d is cancelled.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₂₁, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₁ in accordance with the count value (=1). As aresult, the transistors 91 and 95 in the second connector 4 b are turnedON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₂₂, the high-level self-drive signal Vcomts(1) is supplied tothe wire J₁ via the transistors 73 and 91.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₂₂, the high-level self-drive signal Vcomts(2) is suppliedto the wire J₅ via the transistors 74 and 95.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₂₃, the detection signal Vdet2(1) described in the principle ofthe self-capacitance detection (refer to FIGS. 5 to 8) appears in thewire J₁. Because the transistors 91 and 73 are turned ON at the timingt₂₃, the detection signal Vdet2(1) appearing in the wire J₁ is suppliedto the one of the analog input channels of the amplifier 42 in theanalog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₂₃, the detection signal Vdet2(2) described in the principleof the self-capacitance detection appears in the wire J₅. Because thetransistors 95 and 74 are turned ON at the timing t₂₃, the detectionsignal Vdet2(2) appearing in the wire J₅ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

The detection signals Vdet2(1) and Vdet2(2) illustrated in FIG. 19 donot indicate actual waveforms appearing in the respective wires J₁ andJ₅, but indicate output waveforms in the voltage detector DET in theamplifier 42.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₂₄, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₂ in accordance with the count value (=2). As aresult, the transistors 92 and 96 in the second connector 4 b are turnedON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₂₅, the high-level self-drive signal Vcomts(1) is supplied tothe wire J₂ via the transistors 73 and 92.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₂₅, the high-level self-drive signal Vcomts(2) is suppliedto the wire J₆ via the transistors 74 and 96.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₂₆, the detection signal Vdet2(1) described in the principle ofthe self-capacitance detection appears in the wire J₂. Because thetransistors 92 and 73 are turned ON at the timing t₂₆, the detectionsignal Vdet2(1) appearing in the wire J₂ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₂₆, the detection signal Vdet2(2) described in the principleof the self-capacitance detection appears in the wire J₆. Because thetransistors 96 and 74 are turned ON at the timing t₂₆, the detectionsignal Vdet2(2) appearing in the wire J₆ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₂₇, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₃ in accordance with the count value (=3). As aresult, the transistors 93 and 97 in the second connector 4 b are turnedON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₂₈, the high-level self-drive signal Vcomts(1) is supplied tothe wire J₃ via the transistors 73 and 93.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₂₈, the high-level self-drive signal Vcomts(2) is suppliedto the wire J₇ via the transistors 74 and 97.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₂₉, the detection signal Vdet2(1) described in the principle ofthe self-capacitance detection appears in the wire J₃. Because thetransistors 93 and 73 are turned ON at the timing t₂₉, the detectionsignal Vdet2(1) appearing in the wire J₃ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₂₉, the detection signal Vdet2(2) described in the principleof the self-capacitance detection appears in the wire J₇. Because thetransistors 97 and 74 are turned ON at the timing t₂₉, the detectionsignal Vdet2(2) appearing in the wire J₇ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₃₀, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₄ in accordance with the count value (=4). As aresult, the transistors 94 and 98 in the second connector 4 b are turnedON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₃₁, the high-level self-drive signal Vcomts(1) is supplied tothe wire J₄ via the transistors 73 and 94.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₃₁, the high-level self-drive signal Vcomts(2) is suppliedto the wire J₈ via the transistors 74 and 98.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₃₂, the detection signal Vdet2(1) described in the principle ofthe self-capacitance detection appears in the wire J₄. Because thetransistors 94 and 73 are turned ON at the timing t₃₂, the detectionsignal Vdet2(1) appearing in the wire J₄ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₃₂, the detection signal Vdet2(2) described in the principleof the self-capacitance detection appears in the wire h. Because thetransistors 98 and 74 are turned ON at the timing t₃₂, the detectionsignal Vdet2(2) appearing in the wire J₈ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

From the timing t₂₁ to the timing t₃₂, the detection device 1 canperform detection for one line in the second detector SE2. By repeatingthe processing performed from the timing t₂₁ to the timing t₃₂ the samenumber of times as the number of lines of the detection electrodes 54,the detection device 1 can perform detection for the entire detectionregion of the second detector SE2.

While the analog processor 5 of the detection device 1 according to thefirst embodiment includes the two analog processing channels, thepresent disclosure is not limited thereto. In a case where the analogprocessor 5 includes one analog processing channel, the transistor 72 inthe first connector 4 a may be removed, and the transistors 81 to 88 maybe coupled to the transistor 71. Similarly, the transistor 74 in thesecond connector 4 b may be removed, and the transistors 91 to 98 may becoupled to the transistor 73.

In a case where the analog processor 5 includes three analog processingchannels, another transistor may be provided in parallel with thetransistors 71 and 72 in the first connector 4 a, and some of thetransistors 81 to 88 may be coupled to this transistor. Similarly,another transistor may be provided in parallel with the transistors 73and 74 in the second connector 4 b, and some of the transistors 91 to 98may be coupled to this transistor. This configuration is also applicableto a case where the analog processor 5 includes four or more analogprocessing channels.

Comparative Example

FIG. 20 is a diagram illustrating the detection device according to acomparative example. In a detection device 102 according to thecomparative example, the first detector SE1 is coupled to the substrate61 via the printed circuit board FPC1. The second detector SE2 iscoupled to the substrate 61 via a printed circuit board FPC3. The analogprocessor 5 is provided on the printed circuit board FPC1. An analogprocessor 5 a with the same circuit configuration as that of the analogprocessor 5 is provided on the printed circuit board FPC3. As amodification of the detection device 102, the analog processor 5 a maybe provided on the substrate 51.

The analog processor 5 performs analog processing on the detectionsignals Vdet1 supplied from the first detector SE1, and outputs them tothe host HST. The analog processor 5 a performs analog processing on thedetection signals Vdet2 supplied from the second detector SE2, andoutputs them to the host HST. As illustrated in FIG. 20, the detectiondevice 102 according to the comparative example requires the two analogprocessors 5 and 5 a.

Advantageous Effects

The detection device 1 according to the first embodiment includes theselector 4 that selects one of the first detector SE1 and the seconddetector SE2 in accordance with the control signals supplied from thecontroller 47 in the host HST, and couples the selected one of the firstdetector SE1 and the second detector SE2 to the analog processor 5. Thedetection device 1 includes the selector 4, which allows one analogprocessor 5 to perform analog processing on the detection signals Vdet1supplied from the first detector SE1 and the detection signals Vdet2supplied from the second detector SE2.

With this configuration, the detection device 1 according to the firstembodiment can eliminate the need for the analog processor 5 a of thedetection device 102 according to the comparative example. The circuitsize of the selector 4 is smaller than that of the analog processor 5 a.The detection device 1 can also eliminate the need for the printedcircuit board FPC3 of the detection device 102. Consequently, thedetection device 1 can have a smaller size, save more space, and bemanufactured at a lower cost than the detection device 102 does.

In step with the analog processor 5 including the two analog processingchannels, the selector 4 sequentially selects any one of the wires K₁ toK₄ of the first wire group 111, and couples the selected one to the wireL₂. At the same time, the selector 4 selects any one of the wires K₅ toK₈ of the second wire group 112, and couples the selected one to thewire L₃.

As a result, the detection signals Vdet1(1) supplied from the firstdetector SE1 to the wires K₁ to K₄ are sequentially supplied to the oneof the analog input channels of the amplifier 42 in the analog processor5. At the same time, the detection signals Vdet1(2) supplied from thefirst detector SE1 to the wires K₅ to K₈ are sequentially supplied tothe other of the analog input channels of the amplifier 42 in the analogprocessor 5. Consequently, the detection device 1 can reduce the timerequired for the first detector SE1 to detect the object F1substantially by half.

In step with the analog processor 5 including the two analog processingchannels, the selector 4 sequentially selects any one of the wires J₁ toJ₄ of the third wire group 113, and couples the selected one to the wireL₂. At the same time, the selector 4 selects any one of the wires J₅ toJ₈ of the fourth wire group 114, and couples the selected one to thewire L₃.

As a result, the detection signals Vdet2(1) supplied from the seconddetector SE2 to the wires J₁ to J₄ are sequentially supplied to the oneof the analog input channels of the amplifier 42 in the analog processor5. At the same time, the detection signals Vdet2(2) supplied from thesecond detector SE2 to the wires J₅ to J₈ are sequentially supplied tothe other of the analog input channels of the amplifier 42 in the analogprocessor 5. Consequently, the detection device 1 can reduce the timerequired for the second detector SE2 to detect the object F2substantially by half.

Modification

The first connector 4 a and the second connector 4 b have the samecircuit configuration. Specifically, the transistor 71 of the firstconnector 4 a corresponds to the transistor 73 of the second connector 4b. The transistor 72 of the first connector 4 a corresponds to thetransistor 74 of the second connector 4 b. The transistors 81 to 88 ofthe first connector 4 a correspond to the transistors 91 to 98 of thesecond connector 4 b. The second connector 4 b is coupled to the seconddetector SE2 according to the self-capacitance method. Thus, even whenthe first detector SE1 employs the self-capacitance method, the firstconnector 4 a can be coupled to the first detector SE1. The firstconnector 4 a is coupled to the first detector SE1 according to themutual capacitance method. Thus, even when the second detector SE2employs the mutual capacitance method, the second connector 4 b can becoupled to the second detector SE2.

FIG. 21 is a diagram illustrating the detection device according to amodification of the first embodiment. In a detection device 1 aaccording to the modification of the first embodiment, a first detectorSE1 a is a sensor using the self-capacitance method. The same componentsas those in the first embodiment are denoted by like reference numerals,and the explanation thereof is omitted.

The first detector SE1 a includes a plurality of detection electrodes103. The arrangement of the detection electrodes 103 is the same as thatof the electrodes in the second detector SE2 described with reference toFIG. 16, and thus the explanation thereof is omitted.

The COG 19 does not necessarily include the mutual drive signaltransmitter 7 (refer to FIG. 1) because the first detector SE1 a is asensor using the self-capacitance method.

FIG. 22 is a timing chart of an operation performed by the selector ofthe detection device according to the modification of the firstembodiment. Specifically, FIG. 22 is a timing chart when the selector 4selects the first detector SE1 a out of the first detector SE1 a and thesecond detector SE2, and couples the selected first detector SE1 a tothe analog processor 5.

As illustrated in FIG. 22, when the selection signal SEL supplied fromthe host HST changes from the low level to the high level at timing t₄₀,the transistors 71 and 72 in the first connector 4 a are turned ON. Whenthe inverted selection signal xSEL supplied from the host HST changesfrom the high level to the low level, the transistors 73 and 74 in thesecond connector 4 b are turned OFF. When the reset signal RST changesfrom the high level to the low level, the resetting of the count valuein the first controller 4 c is cancelled.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₄₁, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₁ in accordance with the count value (=1). As a result, thetransistors 81 and 85 in the first connector 4 a are turned ON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₄₂, the high-level self-drive signal Vcomts(1) is supplied tothe wire K₁ via the transistors 71 and 81.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₄₂, the high-level self-drive signal Vcomts(2) is suppliedto the wire K₅ via the transistors 72 and 85.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₄₃, the detection signal Vdet1(1) described in the principle ofthe self-capacitance detection (refer to FIGS. 5 to 8) appears in thewire K₁. Because the transistors 81 and 71 are turned ON at the timingt₄₃, the detection signal Vdet1(1) appearing in the wire K₁ is suppliedto the one of the analog input channels of the amplifier 42 in theanalog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₄₃, the detection signal Vdet1(2) described in the principleof the self-capacitance detection appears in the wire K₅. Because thetransistors 85 and 72 are turned ON at the timing t₄₃, the detectionsignal Vdet1(2) appearing in the wire K₅ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

The detection signals Vdet1(1) and Vdet1(2) illustrated in FIG. 22 donot indicate actual waveforms appearing in the respective wires K₁ andK₅, but indicate output waveforms in the voltage detector DET in theamplifier 42.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₄₄, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₂ in accordance with the count value (=2). As a result, thetransistors 82 and 86 in the first connector 4 a are turned ON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₄₅, the high-level self-drive signal Vcomts(1) is supplied tothe wire K₂ via the transistors 71 and 82.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₄₅, the high-level self-drive signal Vcomts(2) is suppliedto the wire K₆ via the transistors 72 and 86.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₄₆, the detection signal Vdet1(1) described in the principle ofthe self-capacitance detection appears in the wire K₂. Because thetransistors 82 and 71 are turned ON at the timing t₄₆, the detectionsignal Vdet1(1) appearing in the wire K₂ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₄₆, the detection signal Vdet1(2) described in the principleof the self-capacitance detection appears in the wire K₆. Because thetransistors 86 and 72 are turned ON at the timing t₄₆, the detectionsignal Vdet1(2) appearing in the wire K₆ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₄₇, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₃ in accordance with the count value (=3). As a result, thetransistors 83 and 87 in the first connector 4 a are turned ON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₄₈, the high-level self-drive signal Vcomts(1) is supplied tothe wire K₃ via the transistors 71 and 83.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₄₈, the high-level self-drive signal Vcomts(2) is suppliedto the wire K₇ via the transistors 72 and 87.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₄₉, the detection signal Vdet1(1) described in the principle ofthe self-capacitance detection appears in the wire K₃. Because thetransistors 83 and 71 are turned ON at the timing t₄₉, the detectionsignal Vdet1(1) appearing in the wire K₃ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₄₉, the detection signal Vdet1(2) described in the principleof the self-capacitance detection appears in the wire K₇. Because thetransistors 87 and 72 are turned ON at the timing t₄₉, the detectionsignal Vdet1(2) appearing in the wire K₇ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₅₀, the first controller4 c counts the clock signal CLK, and outputs the high-level signal tothe wire M₄ in accordance with the count value (=4). As a result, thetransistors 84 and 88 in the first connector 4 a are turned ON.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the low level to the high level at the nexttiming t₅₁, the high-level self-drive signal Vcomts(1) is supplied tothe wire K₄ via the transistors 71 and 84.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the low level to the high level atthe timing t₅₁, the high-level self-drive signal Vcomts(2) is suppliedto the wire K₈ via the transistors 72 and 88.

When the self-drive signal Vcomts(1) supplied from the one of the analogoutput channels of the self-drive signal transmitter 41 in the analogprocessor 5 changes from the high level to the low level at the nexttiming t₅₂, the detection signal Vdet1(1) described in the principle ofthe self-capacitance detection appears in the wire K₄. Because thetransistors 84 and 71 are turned ON at the timing t₅₂, the detectionsignal Vdet1(1) appearing in the wire K₄ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.

Similarly, when the self-drive signal Vcomts(2) supplied from the otherof the analog output channels of the self-drive signal transmitter 41 inthe analog processor 5 changes from the high level to the low level atthe timing t₅₂, the detection signal Vdet1(2) described in the principleof the self-capacitance detection appears in the wire K₈. Because thetransistors 88 and 72 are turned ON at the timing t₅₂, the detectionsignal Vdet1(2) appearing in the wire K₈ is supplied to the other of theanalog input channels of the amplifier 42 in the analog processor 5.

From the timing t₄₁ to the timing t₅₂, the detection device 1 a canperform detection for one line in the first detector SE1 a. By repeatingthe processing performed from the timing t₄₁ to the timing t₅₂ the samenumber of times as the number of lines of the detection electrodes 103,the detection device 1 a can perform detection for the entire detectionregion of the first detector SE1 a.

The timing chart when the selector 4 selects the second detector SE2 outof the first detector SE1 a and the second detector SE2, and couples theselected second detector SE2 to the analog processor 5 is the same asthat illustrated in FIG. 19 according to the first embodiment, and thusthe explanation and illustration thereof are omitted.

Similarly to the detection device 1 according to the first embodiment,the detection device 1 a according to the modification of the firstembodiment can eliminate the need for the analog processor 5 a of thedetection device 102 according to the comparative example. The circuitsize of the selector 4 is smaller than that of the analog processor 5 a.The detection device 1 a can also eliminate the need for the printedcircuit board FPC3 of the detection device 102. Consequently, thedetection device 1 a can save more space and be manufactured at a lowercost than the detection device 102 does.

Second Embodiment

FIG. 23 is a diagram illustrating a circuit configuration of theselector of the detection device according to a second embodiment of thepresent disclosure. The same components as those in the first embodimentare denoted by like reference numerals, and the explanation thereof isomitted.

A selector 104 does not include the second controller 4 d unlike theselector 4 (refer to FIG. 17) of the detection device 1 according to thefirst embodiment.

The gates of the transistors 91 and 95 are coupled to the firstcontroller 4 c via the wire M₁. When high-level signals are suppliedfrom the first controller 4 c to the wire M₁, the transistors 91 and 95are turned ON.

The gates of the transistors 92 and 96 are coupled to the firstcontroller 4 c via the wire M₂. When high-level signals are suppliedfrom the first controller 4 c to the wire M₂, the transistors 92 and 96are turned ON.

The gates of the transistors 93 and 97 are coupled to the firstcontroller 4 c via the wire M₃. When high-level signals are suppliedfrom the first controller 4 c to the wire M₃, the transistors 93 and 97are turned ON.

The gates of the transistors 94 and 98 are coupled to the firstcontroller 4 c via the wire M₄. When high-level signals are suppliedfrom the first controller 4 c to the wire M₄, the transistors 94 and 98are turned ON.

The timing chart of an operation performed by the selector 104 is thesame as the timing chart (refer to FIGS. 18 and 19) of the operationperformed by the selector 4 of the detection device 1 according to thefirst embodiment, and thus the explanation and illustration thereof areomitted.

Advantageous Effects

The selector 104 according to the second embodiment can have a smallercircuit size by the second controller 4 d than that of the selector 4 ofthe detection device 1 according to the first embodiment. Thisconfiguration can increase the yield of the second detector SE2 (whenthe selector 104 is formed on the substrate 51) or a semiconductorintegrated circuit device in which the selector 104 is formed (when thesemiconductor integrated circuit device provided with the selector 104is mounted on the printed circuit board FPC1).

The number of the wires K is preferably equal to that of the wires Jbecause one first controller 4 c controls the first connector 4 a andthe second connector 4 b. The present disclosure, however, is applicableto a case where the number of the wires K is different from that of thewires J. In this case, another transistor, for example, may be providedin parallel with the transistors 71 and 72 in the first connector 4 a,and wires K₉, K₁₀, . . . may be coupled to this transistor.

Third Embodiment

FIG. 24 is a diagram illustrating a state where the object is in contactwith or in proximity to the detection device according to a thirdembodiment of the present disclosure. FIG. 25 is a side viewschematically illustrating the state where the object is in contact withor in proximity to the detection device according to the thirdembodiment. Specifically, FIG. 25 is a diagram illustrating thedetection device 1 viewed in the direction of an arrow 105 in FIG. 24.The same components as those in the first embodiment are denoted by likereference numerals, and the explanation thereof is omitted.

As illustrated in FIGS. 24 and 25, the object (middle finger of a lefthand in this example) F1 is in contact with or in proximity to thedetection region of the first detector SE1. The object (index finger ofa left hand in this example) F2 is in contact with or in proximity tothe detection region of the second detector SE2.

FIG. 26 is a timing chart of an operation performed by the selector ofthe detection device according to the third embodiment. As illustratedin FIG. 26, when the selection signal SEL supplied from the host HSTchanges from the high level to the low level at timing t₈₀, thetransistors 71 and 72 in the first connector 4 a are turned OFF. Whenthe inverted selection signal xSEL supplied from the host HST changesfrom the low level to the high level, the transistors 73 and 74 in thesecond connector 4 b are turned ON. When the reset signal RST changesfrom the high level to the low level, the resetting of the count valuein the second controller 4 d is cancelled.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₈₁, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₁ in accordance with the count value (=1). As aresult, the transistors 81 and 85 in the second connector 4 b are turnedON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₈₂, a change in the voltage in the driveelectrode block B is transmitted through a route of the drive electrodeCOML, the middle finger F1, a hand 107, and the index finger F2 asindicated by an arrow 106. As a result, the detection signal Vdet2described in the principle of the mutual capacitance detection (refer toFIGS. 2 to 4) appears in the detection electrode 54. Because thetransistors 91 and 73 are turned ON at the timing t₈₂, the detectionsignal Vdet2(1) appearing in the wire J₁ is supplied to the one of theanalog input channels of the amplifier 42 in the analog processor 5.Because the transistors 95 and 74 are also turned ON at the timing t₈₂,the detection signal Vdet2(2) appearing in the wire J₅ is supplied tothe other of the analog input channels of the amplifier 42 in the analogprocessor 5.

The detection signals Vdet2(1) and Vdet2(2) illustrated in FIG. 26 donot indicate actual waveforms appearing in the detection electrode 54,but indicate output waveforms in the voltage detector DET in theamplifier 42.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₈₃, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₂ in accordance with the count value (=2). As aresult, the transistors 92 and 96 in the second connector 4 b are turnedON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₈₄, a change in the voltage in the driveelectrode block B is transmitted through the route of the driveelectrode COML, the middle finger F1, the hand 107, and the index fingerF2 as indicated by the arrow 106. As a result, the detection signalVdet2 described in the principle of the mutual capacitance detectionappears in the detection electrode 54. Because the transistors 92 and 73are turned ON at the timing t₈₄, the detection signal Vdet2(1) appearingin the wire J₂ is supplied to the one of the analog input channels ofthe amplifier 42 in the analog processor 5. Because the transistors 96and 74 are also turned ON at the timing t₈₄, the detection signalVdet2(2) appearing in the wire J₆ is supplied to the other of the analoginput channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₁, the second controller4 d counts the clock signal CLK, and outputs the high-level signal tothe wire N₃ in accordance with the count value (=3). As a result, thetransistors 93 and 97 in the second connector 4 b are turned ON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₈₆, a change in the voltage in the driveelectrode block B is transmitted through the route of the driveelectrode COML, the middle finger F1, the hand 107, and the index fingerF2 as indicated by the arrow 106. As a result, the detection signalVdet2 described in the principle of the mutual capacitance detectionappears in the detection electrode 54. Because the transistors 93 and 73are turned ON at the timing t₈₆, the detection signal Vdet2(1) appearingin the wire J₃ is supplied to the one of the analog input channels ofthe amplifier 42 in the analog processor 5. Because the transistors 97and 74 are also turned ON at the timing t₈₆, the detection signalVdet2(2) appearing in the wire J₇ is supplied to the other of the analoginput channels of the amplifier 42 in the analog processor 5.

When the clock signal CLK supplied from the host HST changes from thelow level to the high level at the next timing t₈₇, the secondcontroller 4 d counts the clock signal CLK, and outputs the high-levelsignal to the wire N₄ in accordance with the count value (=4). As aresult, the transistors 94 and 98 in the second connector 4 b are turnedON.

When the mutual drive signal Vcomtm1 supplied from the COG 19 to onedrive electrode block B in the first detector SE1 changes to the highlevel at the next timing t₈₈, a change in the voltage in the driveelectrode block B is transmitted through the route of the driveelectrode COML, the middle finger F1, the hand 107, and the index fingerF2 as indicated by the arrow 106. As a result, the detection signalVdet2 described in the principle of the mutual capacitance detectionappears in the detection electrode 54. Because the transistors 94 and 73are turned ON at the timing t₈₈, the detection signal Vdet2(1) appearingin the wire J₄ is supplied to the one of the analog input channels ofthe amplifier 42 in the analog processor 5. Because the transistors 98and 74 are also turned ON at the timing t₈₈, the detection signalVdet2(2) appearing in the wire J₈ is supplied to the other of the analoginput channels of the amplifier 42 in the analog processor 5.

From the timing t₈₁ to the timing t₈₈, the detection device 1 canperform detection for one line in the second detector SE2. By repeatingthe processing performed from the timing t₈₁ to the timing t₈₈ the samenumber of times as the number of lines of the detection electrodes 54,the detection device 1 can perform detection for the entire detectionregion of the second detector SE2.

Advantageous Effects

The size of the detection electrodes 54 is smaller than that of thedrive electrodes COML because the second detector SE2 is a sensor thatdetects a fingerprint of the finger F2. Specifically, the length of oneside of the detection electrodes 54 is shorter than that of the shortside of the drive electrodes COML. Due to the small size of thedetection electrodes 54, a large voltage cannot be applied to thedetection electrodes 54. As a result, the amplitude of the self-drivesignals Vcomts applied to the detection electrodes 54 is smaller thanthat of the mutual drive signals Vcomtm1 applied to the drive electrodesCOML. Consequently, according to the first embodiment, the signal/noise(S/N) ratio of the detection signals Vdet2 output from the seconddetector SE2 is smaller than that of the detection signals Vdet1 outputfrom the first detector SE1.

On the other hand, the drive electrodes COML according to the thirdembodiment are supplied with the mutual drive signals Vcomtm1, and thusthe amplitude of the detection signals Vdet2 output from the seconddetector SE2 increases. Consequently, the third embodiment can make theS/N ratio of the detection signals Vdet2 output from the second detectorSE2 larger than that of the detection signals Vdet2 according to thefirst embodiment.

While the first detector SE1 according to the third embodiment employsthe mutual capacitance method in the description above, it may employthe self-capacitance method (refer to FIG. 21). The length of one sideof the detection electrodes 54 is shorter than that of one side of thedetection electrodes 103 (refer to FIG. 21). Due to the small size ofthe detection electrodes 54, a large voltage cannot be applied to thedetection electrodes 54. As a result, the amplitude of the self-drivesignals Vcomts applied to the detection electrodes 54 is smaller thanthat of the self-drive signals Vcomts applied to the detectionelectrodes 103. Consequently, according to the first embodiment, the S/Nratio of the detection signals Vdet2 output from the second detector SE2is smaller than that of the detection signals Vdet1 output from thefirst detector SE1.

Meanwhile, applying the self-drive signals Vcomts having large amplitudeto the detection electrodes 103 increases the amplitude of the detectionsignals Vdet2 output from the second detector SE2. Consequently,according to the third embodiment, the S/N ratio of the detectionsignals Vdet2 output from the second detector SE2 can be made largerthan that of the detection signals Vdet2 according to the firstembodiment.

In a case where the first detector SE1 employs the self-capacitancemethod, the selector 4 selects the first detector SE1 first, and couplesthe first detector SE1 to the analog processor 5. The selector 4 thenoutputs the self-drive signals Vcomts output from the self-drive signaltransmitter 41 in the analog processor 5 to the first detector SE1.Subsequently, the selector 4 selects the second detector SE2, andcouples the second detector SE2 to the analog processor 5. The selector4 then outputs the detection signals Vdet2 output from the seconddetector SE2 to the amplifier 42 in the analog processor 5.

While the finger F1 is the middle finger of a left hand, and the fingerF2 is the index finger of the left hand in the description of the thirdembodiment, the present disclosure is not limited thereto. The finger F1may be a finger of a left hand, and the finger F2 may be a finger of aright hand, for example.

While exemplary embodiments according to the present disclosure havebeen described, the embodiments are not intended to limit the presentdisclosure. The contents disclosed in the embodiments are given by wayof example only, and various changes may be made without departing fromthe spirit of the present disclosure. Appropriate changes made withoutdeparting from the spirit of the invention naturally fall within thetechnical scope of the present disclosure.

The present disclosure includes the following aspects:

(1) A detection device comprising:

a first detector and a second detector each configured to detect that anobject is in contact therewith or in proximity thereto;

a signal processor configured to perform signal processing on adetection signal output from the first detector and the second detector;and

a selector configured to select one of the first detector and the seconddetector, and couple the selected one of the first detector and thesecond detector to the signal processor.

(2) The detection device according to (1), wherein

the selector comprises:

a first connector configured to couple the first detector to the signalprocessor;

a first controller configured to control the first connector to couplethe first detector to the signal processor in accordance with a controlsignal supplied from outside;

a second connector configured to couple the second detector to thesignal processor; and

a second controller configured to control the second connector to couplethe second detector to the signal processor in accordance with thecontrol signal.

(3) The detection device according to (1), wherein

the selector comprises:

a first connector configured to couple the first detector to the signalprocessor;

a second connector configured to couple the second detector to thesignal processor; and

a first controller configured to control the first connector and thesecond connector to couple the first detector to the signal processor orcouple the second detector to the signal processor in accordance with acontrol signal supplied from outside.

(4) The detection device according to (2) or (3), wherein

the signal processor comprises a plurality of signal processing channelsconfigured to input or output a plurality of signals simultaneously,

the first connector comprises a plurality of circuits each configured tocouple one of a plurality of detection electrode groups of the firstdetector to one of the signal processing channels, the circuits couplingthe respective detection electrode groups to the respective signalprocessing channels simultaneously, and

the second connector comprises a plurality of circuits each configuredto couple one of a plurality of detection electrode groups of the seconddetector to one of the signal processing channels, the circuits couplingthe respective detection electrode groups to the respective signalprocessing channels simultaneously.

(5) The detection device according to any one of (1) to (4), wherein

the signal processor is provided on a printed circuit board coupled tothe first detector and the second detector, and

the selector is provided on the second detector or the printed circuitboard.

(6) The detection device according to any one of (1) to (5), wherein

the first detector or the second detector is configured to performself-capacitance detection,

the signal processor comprises a self-drive signal transmitterconfigured to output a self-drive signal for performing theself-capacitance detection, and

the selector is configured to output the self-drive signal to adetection electrode of the selected one of the first detector and thesecond detector, and output the detection signal output from thedetection electrode of the selected one of the first detector and thesecond detector to the signal processor.

(7) The detection device according to any one of (1) to (5), furthercomprising:

a mutual drive signal transmitter configured to output a mutual drivesignal to the first detector for performing mutual capacitance detectionwhen the first detector performs the mutual capacitance detection,wherein

when a first object is in contact with or in proximity to the firstdetector and a second object is in contact with or in proximity to thesecond detector, the selector is configured to select the seconddetector, and output the detection signal output from a detectionelectrode of the second detector to the signal processor.

(8) The detection device according to any one of (1) to (5), wherein

the first detector or the second detector is configured to performself-capacitance detection,

the signal processor comprises a self-drive signal transmitterconfigured to output a self-drive signal for performing theself-capacitance detection, and

when a first object is in contact with or in proximity to the firstdetector and a second object is in contact with or in proximity to thesecond detector, the selector is configured to select the first detectorto output the self-drive signal to a detection electrode of the firstdetector, and then select the second detector to output the detectionsignal output from the second detector to the signal processor.

What is claimed is:
 1. A detection device comprising: a first detectorand a second detector each configured to detect that an object is incontact therewith or in proximity thereto; a signal processor configuredto perform signal processing on a detection signal output from the firstdetector and the second detector; and a selector configured to selectone of the first detector and the second detector, and couple theselected one of the first detector and the second detector to the signalprocessor, wherein the first detector or the second detector isconfigured to perform self-capacitance detection, the signal processorcomprises a self-drive signal transmitter configured to output aself-drive signal for performing the self-capacitance detection, and theselector is configured to output the self-drive signal to a detectionelectrode of the selected one of the first detector and the seconddetector, and output the detection signal output from the detectionelectrode of the selected one of the first detector and the seconddetector to the signal processor.
 2. The detection device according toclaim 1, wherein the selector comprises: a first connector configured tocouple the first detector to the signal processor; a first controllerconfigured to control the first connector to couple the first detectorto the signal processor in accordance with a control signal suppliedfrom outside; a second connector configured to couple the seconddetector to the signal processor; and a second controller configured tocontrol the second connector to couple the second detector to the signalprocessor in accordance with the control signal.
 3. The detection deviceaccording to claim 1, wherein the selector comprises: a first connectorconfigured to couple the first detector to the signal processor; asecond connector configured to couple the second detector to the signalprocessor; and a first controller configured to control the firstconnector and the second connector to couple the first detector to thesignal processor or couple the second detector to the signal processorin accordance with a control signal supplied from outside.
 4. Thedetection device according to claim 1, wherein the signal processor isprovided on a printed circuit board coupled to the first detector andthe second detector, and the selector is provided on the second detectoror the printed circuit board.